Skip to main content
SpringerLink
Log in

Embedded Computer Vision

  • Reference work entry
  • First Online:
Handbook of Hardware/Software Codesign

Abstract

Embedded computer vision is a challenging application domain, requiring high computation rates, high memory bandwidth, and support for a wide range of algorithms. This chapter reviews basic concepts in computer vision, design methodologies for embedded computer vision, platform architectures, and application-specific architectures.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 699.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD 949.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Abbreviations

CGA:

Coarse-Grained Array

CNN:

Convolutional Neural Network

CPU:

Central Processing Unit

CV:

Computer Vision

DRAM:

Dynamic Random-Access Memory

FPGA:

Field-Programmable Gate Array

GOPS:

Giga Operations Per Second

GPU:

Graphics Processing Unit

HSCD:

Hardware/Software Codesign

MAC:

Multiply-Accumulator

MPSoC:

Multi-Processor System-on-Chip

NoC:

Network-on-Chip

QoS:

Quality of Service

RC:

Reconfigurable Cell

RISC:

Reduced Instruction-Set Processor

SPI:

Signal Passing Interface

VLIW:

Very Long Instruction Word

References

  1. Amir A, Zimet L, Sangiovanni-Vincentelli A, Kao S (2005) An embedded system for an eye-detection sensor. Comput Vis Image Underst 98(1):104–123. doi:10.1016/j.cviu.2004.07.009. Special issue on Eye Detection and Tracking

  2. Ansaloni G, Bonzini P, Pozzi L (2011) Egra: a coarse grained reconfigurable architectural template. IEEE Trans Very Large Scale Integr VLSI Syst 19(6):1062–1074. doi:10.1109/TVLSI.2010.2044667

    Article  Google Scholar 

  3. Bouwens F, Berekovic M, Kanstein A, Gaydadjiev G (2007) Architectural exploration of the adres coarse-grained reconfigurable array. In: Reconfigurable computing: architectures, tools and applications. LNCS, vol 4412. Springer, pp 1–13

    Google Scholar 

  4. Casares M, Velipasalar S, Pinto A (2010) Light-weight salient foreground detection for embedded smart cameras. Comput Vis Image Underst 114(11):1223–1237. doi:10.1016/j.cviu.2010.03.023. Special issue on Embedded Vision

  5. Chellappa R, Bhattacharyya S, Saha S, Wolf W, Aggarwal G, Schlessman J, Kianzad V (2005) An architectural level design methodology for embedded face detection. In: Third IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS’05, pp 136–141. doi:10.1145/1084834.1084872

  6. Chetlur S, Woolley C, Vandermersch P, Cohen J, Tran J, Catanzaro B, Shelhamer E (2014) cuDNN: efficient primitives for deep learning. CoRR abs/1410.0759. http://arxiv.org/abs/1410.0759

  7. Clemons J, Jones A, Perricone R, Savarese S, Austin T (2011) Effex: an embedded processor for computer vision based feature extraction. In: 2011 48th ACM/EDAC/IEEE design automation conference (DAC), pp 1020–1025

    Google Scholar 

  8. Farabet C, Martini B, Corda B, Akselrod P, Culurciello E, LeCun Y (2011) Neuflow: a runtime reconfigurable dataflow processor for vision. In: 2011 IEEE Computer Society conference on computer vision and pattern recognition workshops (CVPRW), pp 109–116. doi:10.1109/CVPRW.2011.5981829

  9. Gudis E, Lu P, Berends D, Kaighn K, van der Wal G, Buchanan G, Chai S, Piacentino M (2013) An embedded vision services framework for heterogeneous accelerators. In: 2013 IEEE conference on computer vision and pattern recognition workshops (CVPRW), pp 598–603. doi:10.1109/CVPRW.2013.90

  10. Horprasesert T, Harwood D, Davis LS (1999) A statistical approach for real-time robust background subtraction and shadow detection. In: IEEE international conference on computer vision FRAME-RATE workshop

    Google Scholar 

  11. Texas Instruments (2015) TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual, SPRUGX8C, March 2015

    Google Scholar 

  12. Krizhevsky A, Sutskever I, Hinton GE (2013) Imagenet classification with deep convolutional neural networks. In: Pereira F, Burges CJC, Bottou L, Weinberger KQ (eds) Advances in neural information processing systems 25. NIPS 2012: neural information processing systems. https://books.google.com/books?id=glsymwEACAAJ

  13. Lanuzza M, Perri S, Corsonello P, Margala M (2007) A new reconfigurable coarse-grain architecture for multimedia applications. In: 2007 second NASA/ESA conference on adaptive hardware and systems, AHS 2007, pp 119–126. doi:10.1109/AHS.2007.10

    Google Scholar 

  14. Lee MH, Singh H, Lu G, Bagherzadeh N, Kurdahi FJ, Filho EM, Alves VC (2000) Design and implementation of the morphosys reconfigurable computing processor. J VLSI Signal Process Syst Signal Image Video Technol 24(2):147–164

    Article  Google Scholar 

  15. Lucas B, Kanade T (1981) An iterative image registration technique with an application to stereo vision. In: International joint conference on artificial intelligence. AAAI

    Google Scholar 

  16. nVidia (2015) GPU-based deep learning inference: a performance and power analysis. Technical report

    Google Scholar 

  17. Ovtcharov K, Rowase O, Kim JY, Fowers J, Straus K, Chung ES (2015) Accelertaing deep convolutional neural networks using specialized hardware. http://research.microsoft.com/pubs/240715/CNN

  18. Ozer B, Wolf M (2014) A train station surveillance system: challenges and solutions. In: 2014 IEEE conference on computer vision and pattern recognition workshops, pp 652–657. doi:10.1109/CVPRW.2014.99

  19. Park H, Park Y, Mahlke S (2009) Polymorphic pipeline array: a flexible multicore accelerator with virtualized execution for mobile multimedia applications. In: 42nd annual IEEE/ACM international symposium on microarchitecture, 2009 MICRO-42, pp 370–380

    Google Scholar 

  20. Saha S, Puthenpurayil S, Schlessman J, Bhattacharyya S, Wolf W (2008) The signal passing interface and its application to embedded implementation of smart camera applications. Proc IEEE 96(10):1576–1587. doi:10.1109/JPROC.2008.928744

    Article  Google Scholar 

  21. Saha S, Bambha NK, Bhattacharyya SS (2010) Design and implementation of embedded computer vision systems based on particle filters. Comput Vis Image Underst 114(11):1203–1214. doi:10.1016/j.cviu.2010.03.018. Special issue on Embedded Vision

  22. Schlessman J, Wolf M (2015) Tailoring design for embedded computer vision applications. Computer 48(5):58–62. doi:10.1109/MC.2015.145

    Article  Google Scholar 

  23. Soderquist P, Leeser M (1997) Division and square root: choosing the right implementation. Micro IEEE 17(4):56–66. doi:10.1109/40.612224

    Article  Google Scholar 

  24. Stein G, Rushinek E, Hayun G, Shashua A (2005) A computer vision system on a chip: a case study from the automotive domain. In: Proceedings of IEEE Computer Society conference on computer vision and pattern recognition – workshops (CVPR 2005), pp 130–130. doi:10.1109/CVPR.2005.387

  25. Tabkhi H, Bushey R, Schirner G (2014) Function-level processor (FLP): a high performance, minimal bandwidth, low power architecture for market-oriented MPSoCs. IEEE Embed Syst Lett 6(4):65–68. doi:10.1109/LES.2014.2327114

    Article  Google Scholar 

  26. van der Wolf P, Geuzebroek J (2011) SoC infrastructures for predictable system integration. In: Design, automation test in Europe conference exhibition (DATE), 2011, pp 1–6. doi:10.1109/DATE.2011.5763146

  27. van der Wolf P, Henriksson T (2008) Video processing requirements on SoC infrastructures. In: Design, automation and test in Europe, 2008, DATE ’08, pp 1124–1125. doi:10.1109/DATE.2008.4484827

  28. Viola P, Jones M (2001) Rapid object detection using a boosted cascade of simple features. In: Proceedings of the 2001 IEEE Computer Society conference on computer vision and pattern recognition, CVPR 2001, vol 1, pp I–511–I–518. doi:10.1109/CVPR.2001.990517

  29. Weber WD, Chou J, Swarbrick I, Wingard D (2005) A quality-of-service mechanism for interconnection networks in system-on-chips. In: Proceedings of the design, automation and test in Europe, vol 2, pp 1232–1237. doi:10.1109/DATE.2005.33

  30. Wolf W, Ozer B, Lv T (2002) Smart cameras as embedded systems. IEEE Comput 35(9):48–53

    Article  Google Scholar 

  31. Wolf W, Jerraya A, Martin G (2008) Multiprocessor system-on-chip (MPSoC) technology. IEEE Trans Comput Aided Des Integr Circuits Syst 27(10):1701–1713. doi:10.1109/TCAD.2008.923415

    Article  Google Scholar 

  32. Xu J, Wolf W, Henkel J, Chakradhar S, Lv T (2004) A case study in networks-on-chip design for embedded video. In: Proceedings of the design, automation and test in Europe conference and exhibition, vol 2, pp 770–775. doi:10.1109/DATE.2004.1268973

  33. Xu J, Wolf W, Henkel J, Chakradhar S (2006) A design methodology for application-specific networks-on-chip. ACM Trans Embed Comput Syst 5(2):263–280. doi:10.1145/1151074.1151076

    Article  Google Scholar 

  34. Yang M, Crenshaw J, Augustine B, Mareachen R, Wu Y (2010) Adaboost-based face detection for embedded systems. Comput Vis Image Underst 114(11):1116–1125. doi:10.1016/j.cviu.2010.03.010. Special issue on Embedded Vision

  35. Zhang C, Li P, Sun G, Guan Y, Xiao B, Cong J (2015) Optimizing FPGA-based accelerator design for deep convolutional neural networks. In: Proceedings of the 2015 ACM/SIGDA international symposium on field-programmable gate arrays, FPGA ’15, pp 161–170. ACM, New York. doi:10.1145/2684746.2689060

Download references

Author information

Authors and Affiliations

  1. School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA

    Marilyn Wolf

Authors
  1. Marilyn Wolf
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Marilyn Wolf .

Editor information

Editors and Affiliations

  1. Department of Computer Science and Engineering, Seoul National University, Seoul, Korea (Republic of)

    Soonhoi Ha

  2. Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany

    Jürgen Teich

Rights and permissions

Reprints and permissions

Copyright information

© 2017 Springer Science+Business Media Dordrecht

About this entry

Cite this entry

Wolf, M. (2017). Embedded Computer Vision. In: Ha, S., Teich, J. (eds) Handbook of Hardware/Software Codesign. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7267-9_40

Download citation

Publish with us

Policies and ethics

Search

Navigation