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Reliability of 3D NAND Flash Memories

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3D Flash Memories

Abstract

In this chapter the main reliability mechanisms affecting 3D NAND memories will be addressed, providing a comparison between 3D FG and 3D CT devices in terms of reliability and expected performances. Starting from an analysis of basic reliability issues related to both physical and architectural aspects affecting NAND memories, the specific physical mechanisms impacting the reliability of 2D CT NAND will be addressed. Then, a review of the main problems experimentally observed in different 3D CT cell concepts is reported. Finally, 3D FG memory concept is briefly introduced in order to understand the related reliability implications, and a comparison between 3D CT and 3D FG arrays is provided in terms of reliability and expected performances.

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References

  1. R. Micheloni et al., Inside NAND Flash Memories (Springer, 2010)

    Google Scholar 

  2. C. Lee et al., Multi-level NAND flash memory with 63 nm-node TANOS (Si-Oxide-SiN-Al2O3-TaN) cell structure, in VLSI Symposium Technical Digest (2006), pp. 21–22

    Google Scholar 

  3. G. Van Den Bosch, Physics and reliability of 2D and 3D SONOS devices, in IEEE International Memory Workshop (IMW), Tutorial, 18–21 May 2014

    Google Scholar 

  4. A. Grossi et al., Bit error rate analysis in charge trapping memories for SSD applications, in IEEE International Reliability Physics Symposium (IRPS), June 2014, pp. MY.7.1–MY.7.5

    Google Scholar 

  5. Y. Cai et al., Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling, in Design, Automation Test in Europe Conference Exhibition (DATE), Mar 2013, pp. 1285–1290

    Google Scholar 

  6. A. Chimenton et al., A statistical model of erratic behaviors in NAND flash memory arrays. IEEE Trans. Electron Devices 58, 3707–3711 (2011)

    Article  Google Scholar 

  7. T. Ong et al., Erratic erase in ETOX TM flash memory array, in Proceedings of VLSI Symposium Technical, pp. 83–84 (1993)

    Google Scholar 

  8. C. Dunn et al., Flash EPROM disturb mechanisms, in Proceedings of IEEE International Reliability Physics Symposium (IRPS), Apr 1994, pp. 299–308

    Google Scholar 

  9. C. Zambelli et al., Analysis of edge wordline disturb in multimegabit charge trapping flash NAND arrays, in IEEE International Reliability Physics Symposium (IRPS), 10–14 Apr 2011, pp. MY.4.1–MY.4.5

    Google Scholar 

  10. J. Lee, C. Lee, M. Lee, H. Kim, K. Park, W. Lee, A new programming disturbance phenomenon in NAND flash memory by source/drain hot electrons generated by GIDL current, in Proceedings of the NVSM Workshop (2006), pp. 31–33

    Google Scholar 

  11. A. Arreghini et al., Experimental extraction of the charge centroid and of the charge type in the P/E operations of the SONOS memory cells, in IEDM 2006 Technical Digest (2006), pp. 499–502

    Google Scholar 

  12. L. Vandelli et al., Role of holes and electrons during erase of TANOS memories: evidences for dipole formation and its impact on reliability, in IEEE International Reliability Physics Symposium (IRPS), 2–6 May 2010, pp. 731–737

    Google Scholar 

  13. A. Arreghini et al., Characterization and modeling of long term retention in SONOS non volatile memories, in Solid State Device Research Conference, 37th European ESSDERC, 11–13 Sept 2007, pp. 406–409

    Google Scholar 

  14. C.-P. Chen et al., Study of fast initial charge loss and it’s impact on the programmed states VT distribution of charge-trapping NAND flash, in IEEE International Electron Devices Meeting (IEDM) (2010), pp. 5.6.1–5.6.4

    Google Scholar 

  15. J.K. Park et al., Origin of transient Vth shift after erase and its impact on 2D/3D structure charge trap flash memory cell operations, in IEEE International Electron Devices Meeting (IEDM), 10–13 Dec 2012, pp. 2.4.1–2.4.4

    Google Scholar 

  16. H. Park et al., Charge loss in TANOS devices caused by Vt sensing measurements during retention, in IEEE International Memory Workshop (IMW), 16–19 May 2010, pp. 1–2

    Google Scholar 

  17. H. Tanaka et al., Bit cost scalable technology with punch and plug process for ultra high density flash memory, in IEEE Symposium on VLSI Technology, 12–14 June 2007, pp. 14–15

    Google Scholar 

  18. J. Jang et al., Vertical cell array using TCAT (terabit cell array transistor) technology for ultra high density NAND flash memory, in IEEE Symposium on VLSI Technology, 16–18 June 2009, pp. 192–193

    Google Scholar 

  19. S.J. Whang et al., Novel 3-dimensional dual control-gate with surrounding floating-gate (DC-SF) NAND flash cell for 1 Tb file storage application, in IEEE International Electron Devices Meeting (IEDM), 6–8 Dec 2010, pp. 29.7.1–29.7.4

    Google Scholar 

  20. W. Kim et al., Multi-layered vertical gate NAND flash overcoming stacking limit for terabit density storage, in IEEE Symposium on VLSI Technology, 16–18 June 2009, pp. 188–189

    Google Scholar 

  21. A. Goda et al., Scaling directions for 2D and 3D NAND cells, in IEEE International Electron Devices Meeting (IEDM), 10–13 Dec 2012, pp. 2.1.1–2.1.4

    Google Scholar 

  22. H.T. Lue et al., 3D vertical gate NAND device and architecture, in IEEE International Memory Workshop (IMW), Tutorial, 18–21 May 2014

    Google Scholar 

  23. Y. Fukuzumi et al., Optimal integration and characteristics of vertical array devices for ultra-high density, bit-cost scalable flash memory, in IEDM Technical Digest (2007), pp. 449–452

    Google Scholar 

  24. Y. Kim et al., Coding scheme for 3D vertical flash memory, in IEEE International Conference on Communications (ICC), 8–12 June 2015

    Google Scholar 

  25. E. Nowak et al., In-depth analysis of 3D silicon nanowire SONOS memory characteristics by TCAD simulations, in IEEE International Memory Workshop (IMW), 16–19 May 2010, pp. 1–4

    Google Scholar 

  26. H.-T. Lue et al., Understanding STI edge fringing field effect on the scaling of charge-trapping (CT) NAND flash and modeling of incremental step pulse programming (ISPP), in IEDM Technical Digest (2009), pp. 839–842

    Google Scholar 

  27. S.M. Amoroso et al., Semi-analytical model for the transient operation of gate-all-around charge-trap memories. IEEE Trans. Electron Devices 58(9), 3116–3123 (2011)

    Article  Google Scholar 

  28. X. Li et al., Investigation of charge loss mechanisms in 3D TANOS cylindrical junction-less charge trapping memory, in IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 28–31 Oct 2014, pp. 1–3

    Google Scholar 

  29. Z. Lun et al., Investigation of retention behavior for 3D charge trapping NAND flash memory by 2D self-consistent simulation, in International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 9–11 Sept 2014, pp. 141–144

    Google Scholar 

  30. Y. Yanagihara et al., Control gate length, spacing and stacked layer number design for 3D-stackable NAND flash memory, in IEEE International Memory Workshop (IMW), 20–23 May 2012, pp. 1–4

    Google Scholar 

  31. E.-S. Choi et al., Device considerations for high density and highly reliable 3D NAND flash cell in near future, in IEEE International Electron Devices Meeting (IEDM), 10–13 Dec 2012, pp. 9.4.1–9.4.4

    Google Scholar 

  32. M.K. Seo et al., The 3-dimensional vertical FG NAND flash memory cell arrays with the novel electrical S/D technique using the extended sidewall control gate (ESCG), in IEEE International Memory Workshop (IMW), May 2010, pp. 146–149

    Google Scholar 

  33. S. Aritome et al., Advanced DC-SF cell technology for 3-D NAND flash. IEEE Trans. Electron Devices 60(4), 1327–1333 (2013)

    Article  Google Scholar 

  34. S.J. Whang et al., Novel 3-dimensional dual control-gate with surrounding floating-gate (DC-SF) NAND flash cell for 1Tb file storage application, in IEEE International Electron Devices Meeting (IEDM), 6–8 Dec 2010, pp. 29.7.1–29.7.4

    Google Scholar 

  35. M.K. Seo et al., A novel 3-D vertical FG NAND flash memory cell arrays using the separated sidewall control gate (S-SCG) for highly reliable MLC operation, in IEEE International Memory Workshop (IMW), 22–25 May 2011, pp. 1–4

    Google Scholar 

  36. K. Parat et al., A floating gate based 3D NAND technology with CMOS under array in IEEE International Electron Devices Meeting (IEDM), 7–9 Dec 2015

    Google Scholar 

  37. B. Prince, 3D vertical NAND flash revolutionary or evolutionary, in IEEE International Memory Workshop, Tutorial, 17–20 May 2015

    Google Scholar 

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Correspondence to A. Grossi .

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Grossi, A., Zambelli, C., Olivo, P. (2016). Reliability of 3D NAND Flash Memories. In: Micheloni, R. (eds) 3D Flash Memories. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7512-0_2

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  • DOI: https://doi.org/10.1007/978-94-017-7512-0_2

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