Abstract
This paper aims to parallelize the simulated annealing algorithm used for the placement of circuit elements in the logic blocks of an FPGA. It intends to introduce the simulated annealing algorithm and the placement problem, analyzes the complexities involved, and justifies the use of simulated annealing as the algorithm for placement ahead of other algorithms. It explains the accuracy of the simulated annealing algorithm using a simple example which, also aims to explore parallelization techniques currently in use, such as parallel moves, area-based partitioning, Markov chains, and suggests possible improvements in the same using a combination of the above, using GPGPUs and investigate further the effects of move biasing. Also, the VPR (versatile placement and routing) CAD tool is introduced and key functions related to placement are explained [1]. The use of GPGPUs to achieve the required parallelism and speedup is discussed, along with the difficulties involved in implementing the same.
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The authors thank Sri.T.V. Bala Krishna Murthy who gave the entire support to write this article in such a good manner.
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Rajesh Eswarawaka, Pagadala, P.K., Eswara Reddy, B., Rao, T. (2016). Parallelization of Simulated Annealing Algorithm for FPGA Placement and Routing. In: Pant, M., Deep, K., Bansal, J., Nagar, A., Das, K. (eds) Proceedings of Fifth International Conference on Soft Computing for Problem Solving. Advances in Intelligent Systems and Computing, vol 436. Springer, Singapore. https://doi.org/10.1007/978-981-10-0448-3_84
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DOI: https://doi.org/10.1007/978-981-10-0448-3_84
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