Abstract
Stencil computations are a class of computational kernels which update array elements according to some stencil patterns, and they have drawn more attentions recently. The Intel Xeon Phi coprocessor, which is designed for high performance computing, has not been fully evaluated for stencil computations. In this paper, we present a series of optimizations to accelerate the 3-D 7-point stencil code on Intel Xeon Phi coprocessor. We focus on how to exploit the performance potential of many cores and wide-vector unit in each core. In order to exploit data locality, we use loop tiling and we propose a method for calculating the block size while tiling. The achieved performance brings a speedup of 211.6 in comparison with the serial code.
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Acknowledgments
The work described in this paper is partially supported by the project of National Science Foundation of China under grant No.61170046 and No.61402495.
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Feng, L., Dong, Y., Li, C., Jiang, H. (2016). High Performance Stencil Computations for Intel\(^{\normalsize \circledR }\) Xeon Phi™ Coprocessor. In: Wu, J., Li, L. (eds) Advanced Computer Architecture. ACA 2016. Communications in Computer and Information Science, vol 626. Springer, Singapore. https://doi.org/10.1007/978-981-10-2209-8_10
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DOI: https://doi.org/10.1007/978-981-10-2209-8_10
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