Abstract
As the manufacturing processes become more and more advanced as per Moore’s law, precise control of silicon process is becoming more and more challenging. This increases the probability of defects and has brought a necessity for testing to ensure fault-free products, making the testing of a chip more complex causing testing challenges.
With large number of transistors, in multiples of thousands being integrated in one chip, multiple stuck-at faults may exist, because of which fault masking and reinforcing effects may come into effect. This may lead to the failure of approaches like Single Location at a Time (SLAT) and restricted single sensitized paths. To counter this, the notion of fault element is used to take into account multiple fault models and use a fault element graph (FEG) to consider fault masking and reinforcing effects among multiple faults. To identify these faults, appropriate test patterns need to be generated that would carry the effect of the fault to the primary output. The test patterns are chosen such that switching power is made to be a minimum.
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Gokkul Nath, T.S., Midhila, E.R., Swaminathan, A., Lekshmi, B., Anita, J.P. (2016). Diagnosis of Multiple Stuck-at Faults Using Fault Element Graph with Reduced Power. In: Mueller, P., Thampi, S., Alam Bhuiyan, M., Ko, R., Doss, R., Alcaraz Calero, J. (eds) Security in Computing and Communications. SSCC 2016. Communications in Computer and Information Science, vol 625. Springer, Singapore. https://doi.org/10.1007/978-981-10-2738-3_36
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DOI: https://doi.org/10.1007/978-981-10-2738-3_36
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