Abstract
The design of high-radix switch chips is becoming a challenging research field in EHPC (Exascale High-Performance Computing). Recent development of silicon photonic and 3D integration technologies has inspired new methods of designing high-radix switch chips. In this paper, we propose a high-radix switch architecture called Grahpein, which improves the radix and bandwidth while lowering switch chips power consumption by 3D integration and silicon photonic technology. The simulation result also shows that the average latencies under both random and hotspot patterns are less than 10 cycles, and the throughput under random pattern is more than 95%. Compared to hi-rise architecture, the proposed architecture ensures the packets from different source ports receive fairer service, thereby yielding more concentrated latency distribution. In addition, the power consumption of the Graphein chip is about 19.2 W, which totally satisfies the power constraint on a high-radix switch chip.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
International Technology Roadmap for Semiconductors, ITRS
SB7700: 36-port Non-blocking Managed EDR 100 Gb/s InfiniBand Switch, Mellanox Technologies (2015)
OIF Next Generation Interconnect Framework, April 2013
Birrittella, M.S., Debbage, M.: Intel@ Omni-Path Architecture: Enabling Scalable, High Performance Fabrics. IEEE (2015)
Biberman, A., Bergman, K.: Optical interconnection networks for high-performance computing systems. IOP sci. Rep. Prog. Phys. 75, 046402 (2012). 15 pp
Ophir, N., Mineo, C., Mountain, D., Bergman, K.: Silicon photonic microring links for high-bandwidth-density, low-power-chip I/O. In: IEEE MICRO, January 2013
Koonath, P., Jalali, B.: Multilayer 3-d photonics in silicon. Opt. Express 15(20), 12686C12691 (2007)
Morris Jr., R.W.: The three-dimensional stacked nanophotonic network-on-chip architecture with minimal reconfiguration. IEEE Trans. Comput. 63(1), 243–255 (2014)
Dang, D., Patra, B., Mahapatra, R., A 2-layer laser multiplexed photonic network-on-chip. In: 16th International Symposium on Quality Electronic Design (2015)
Pavlidis, V., Friedman, E.: Three-dimensional Integrated Circuit Design. Morgan Kaufmann Pub, San Francisco (2009)
Vangal, S., et al.: An 80-Tile 1.28 TFLOPS network-on-chip in 65 nm CMOS. In: IEEE International Solid State Circuits Conference, February 2007
Bernstein, K., et al.: Interconnects in the third dimension: design challenges for 3D ICs. In: DAC (2007)
Patti, R.S.: Three-dimensional integrated circuits and the future of system-on-chip design. In: Proceedings of IEEE, vol. 94, no. 6, June 2006
Jeloka, S., Das, R.: Hi-Rise: a high-radix switch for 3D integration with single-cycle arbitration. In: MICRO (2014)
Kim, J., Balfour, J., Dally, W.: Flattened butterfly topology for on-chip networks. In: MICRO (2007)
Kim, J., Dally, W.J.: Technology-driven, highly-scalable dragonfly topology. In: ISCA (2008)
Scott, S., Abts, D., Kim, J.: The black widow high-radix clos network. In: ISCA (2006)
Binkert, N., Davis, Al.: The role of optics in future high radix switch design. In: ISCA (2011)
Vantrease Corona, D., et al.: System implications of emerging nanophotonic technology. In: ISCA (2008)
Pan Flexishare, Y., et al.: Channel sharing for an energy-efficient nanophotonic crossbar. In: HPCA (2010)
Vantrease, D., et al.: Light speed arbitration and flow control for nanophotonic interconnects. In: MICRO (2009)
Joshi, A., Batten, C., Kwon, Y.: Silicon-photonic clos networks for global on-chip communication. In: IEEE International Symposium on Network-on-Chip (NOCS), San Diego, CA (2009)
Acknowledgment
This work was partially supported by 863 Program of China (2015AA015302), NSFC (61572509).
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Jie, J., Liquan, X., Mingche, L., Shi, X. (2016). A High-Radix Switch Architecture Based on Silicon Photonic and 3D Integration. In: Xu, W., Xiao, L., Li, J., Zhang, C., Zhu, Z. (eds) Computer Engineering and Technology. NCCET 2016. Communications in Computer and Information Science, vol 666. Springer, Singapore. https://doi.org/10.1007/978-981-10-3159-5_17
Download citation
DOI: https://doi.org/10.1007/978-981-10-3159-5_17
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-3158-8
Online ISBN: 978-981-10-3159-5
eBook Packages: Computer ScienceComputer Science (R0)
