Abstract
Discrete cosine transform (DCT) and its inverse (IDCT) play a key role in image and video systems. In this paper, we propose an efficient DCT/IDCT architecture based on adaptive recoding coordinate rotation digital computer (ARC), which has been validated on an FPGA platform. Compared to the state-of-the-art DCT, the proposed architecture dissipates 8.2% less power and improves PSNR by 3.21 dB while maintaining nearly the same area and speed. The proposed architecture uses 37.6% less hardware resources, saves 31.6% in power dissipation, provides a 2.15 times speed-up and improves PSNR slightly when compared with the newest DCT/IDCT architecture.
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Acknowledgments
This work is supported by Xilinx. We also would like to thank Jianfeng Zhang and the reviewer for their revisions and suggestions.
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Feng, Y., Zhang, J., Liu, H. (2016). A Novel Low-Power and High-PSNR Architecture Based on ARC for DCT/IDCT. In: Xu, W., Xiao, L., Li, J., Zhang, C., Zhu, Z. (eds) Computer Engineering and Technology. NCCET 2016. Communications in Computer and Information Science, vol 666. Springer, Singapore. https://doi.org/10.1007/978-981-10-3159-5_6
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DOI: https://doi.org/10.1007/978-981-10-3159-5_6
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