Abstract
In this paper, a high-throughput decoder architecture for quasi-cyclic low density parity check (QC-LDPC) codes is presented. Using the Normalized Min-Sum algorithm and the turbo-decoding message-passing algorithm, the proposed design expanded degree of parallelism to improve the throughput at a cost of hardware resource usage. Based on the proposed architecture, we implemented a (8176, 7154) Euclidian geometry-based QC-LDPC code decoder on a Xilinx Kintex7 (XC7K325T-2) board. The FPGA implementation results show that the decoder can achieve a total decoding throughput of 1.6 Gbps at the clock frequency of 105Mth at 10 iterations.
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Acknowledgements
This work is supported by the National Science Foundation of China (Grant No. 61373032, Grant No. 61472244) and Innovation Program of Shanghai Municipal Education Commission (Grant No. 14ZZ018).
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© 2016 Springer Nature Singapore Pte Ltd.
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Liao, R., Fu, Y., Liu, T. (2016). FPGA-Based High Throughput TDMP LDPC Decoder. In: Xu, W., Xiao, L., Li, J., Zhang, C., Zhu, Z. (eds) Computer Engineering and Technology. NCCET 2016. Communications in Computer and Information Science, vol 666. Springer, Singapore. https://doi.org/10.1007/978-981-10-3159-5_9
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DOI: https://doi.org/10.1007/978-981-10-3159-5_9
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