Abstract
This paper mainly researches the accelerating digital watermarking algorithm based on SOC. A digital watermarking system for software and hardware co-design is built by Xilinx high level synthesis tool HLS. DCT/IDCT algorithm is programmed by C++ language. After simulation and synthesis, HLS generates RTL code suitable for either ASIC or FPGA synthesis tools. 86.5% of the delay time is saved by optimizing the design. The hardware acceleration is realized by parallel processing, which is increasing the hardware design cost to improve the processing performance of time. The utilization of hardware system is improved by pipeline, the waiting time is reduced and each hardware module is in high efficiency. DCT-based invisible digital watermarking system IP core on SOC becomes the ideal choice for embedded real-time visual surveillance system for it can make use of existing manufacturing processes, and the hardware implementation of the system execution speed about 200 times higher than that of software.
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Chen, J., Fan, H., Sun, Y., Ma, H. (2017). Accelerating Digital Watermarking Algorithm Based on SOC. In: Yang, X., Zhai, G. (eds) Digital TV and Wireless Multimedia Communication. IFTC 2016. Communications in Computer and Information Science, vol 685. Springer, Singapore. https://doi.org/10.1007/978-981-10-4211-9_3
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DOI: https://doi.org/10.1007/978-981-10-4211-9_3
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