Abstract
Double Date Rate (DDR) SDRAM is the double rate synchronous dynamic random memory. It can sample twice on the rising and falling edges of the clock. Therefore, its sampling rate is theoretically twice the conventional SDRAM. However, due to other time cost, its bandwidth utilization is great lower than the theoretical value. DDR3 is the third generation and it has lower power consumption and higher sampling rate, so it is more suitable for data buffers than other SDRAM. Xilinx offers an IP core called MIG to simplify the interface of DDR3 SDRAM. This paper analyzes the problem of low bandwidth utilization, proposes an improved method, and designs a controller similar to the FIFO architecture based on the MIG core. In this way, the user-oriented interface is further simplified and the designer can use it easily. In addition, it has better portability.
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References
Jia, M., Gu, X., Guo, Q., Xiang, W., Zhang, N.: Broadband hybrid satellite-terrestrial communication systems based on cognitive radio toward 5G. IEEE Wirel. Commun. 23(6), 96–106 (2017)
Pan, G., Li, L., Ou, G., Qiang, D., Xie, L.: Design and implementation of a DDR3-based memory controller. In: Third International Conference on Intelligent System Design and Engineering Applications, pp. 540–543 (2013)
Wang, B., Du, J., Xin, B., Xing, T.: High bandwidth memory interface design based on DDR3 SDRAM and FPGA. In: SoC Design Conference, pp. 253–254. IEEE (2015)
Wang, B.P., Du, J.S., Tian, X., Bi, X.: Simulation and analysis of DDR3 bus based on fly-by topology with cadence. Appl. Mech. Mater. 670–671, 1447–1453 (2014)
Gao, F., Zhang, R., Liang, Y.C.: Optimal channel estimation and training design for two-way relay networks. IEEE Trans. Commun. 57(10), 3024–3033 (2009)
Xilinx. 7 Series FPGAs Memory Interface Solutions [M/OL]. UG586 25 July 2012
Acknowledgement
This work was supported by the Open Research Fund of State Key Laboratory of Space-Ground Integrated Information Technology under grant No. 2015_SGIIT_KFJJ_TX_02 and the National Science Foundations of China (No. 61671183, 91438205, 61771183).
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Wang, X., Shen, L., Jia, M. (2019). The Design and Optimization of DDR3 Controller Based on FPGA. In: Liang, Q., Mu, J., Jia, M., Wang, W., Feng, X., Zhang, B. (eds) Communications, Signal Processing, and Systems. CSPS 2017. Lecture Notes in Electrical Engineering, vol 463. Springer, Singapore. https://doi.org/10.1007/978-981-10-6571-2_211
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DOI: https://doi.org/10.1007/978-981-10-6571-2_211
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