Abstract
The excellent error correction performance of Low-Density Parity Check code has made it widely used in many modern communication systems, including space communication system. This paper describes a design and FPGA implementation of a quasi-cyclic LDPC decoder based on Min-Sum Algorithm. The partially parallel design solves the contradiction between the consumption of hardware resource and decoding efficiency. The decoder achieves up to a BER of 10−3 at 4 dB, and a throughput of 300 Mbps per iteration for a code length of 8176.
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Acknowledgments
This work was supported by the Fundamental Research Funds for the Center Universities (Grant No. HIT.MKSTISP.2016 13).
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Zhao, H., Zhang, H. (2019). Design and FPGA Implementation of a Quasi-Cyclic LDPC Decoder. In: Liang, Q., Mu, J., Jia, M., Wang, W., Feng, X., Zhang, B. (eds) Communications, Signal Processing, and Systems. CSPS 2017. Lecture Notes in Electrical Engineering, vol 463. Springer, Singapore. https://doi.org/10.1007/978-981-10-6571-2_222
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DOI: https://doi.org/10.1007/978-981-10-6571-2_222
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