Implementation of a Pipeline Large-FFT Processor Based on the FPGA

Abstract

This paper presents a scheme of pipeline large Fast Fourier Transform (FFT) processor on FPGA which is based on radix-2 Multi-path Delay Commutator architecture. For N-point FFT, the design uses log₂N counters to control the working state of each stage of FFT and shift registers with storage of size 3N/2 − 2 to cache the intermediate calculated data. Compared with the dual-port RAM pipeline architecture with 2N memory sizes, the complexity of logical control is low because the intermediate calculated data is not stored and read by RAMs. The consumption of the memory resources is reduced. The proposed design is implemented of 1024-point FFT on an Altera Stratix II EP2S30F48414N FPGA. The highest operating frequencies are 250 MHz, and the time required to calculate FFT is about 6.3 ms. The results show that the design of the FFT processor meets the real-time requirement, and can be applied to large-point FFT computing.