Abstract
Adders are invariably present in arithmetic units, and they are needed for implementing the operations: addition/subtraction, multiplication, division, etc. Due to the crucial role of adder in arithmetic unit, it is necessary to satisfactorily characterize the maximum propagation delay of the adder. To characterize 4-bit Ripple Carry Adder (RCA), ideally 261,632 input transitions are required [1], which is a humongous number. In this paper, we have proposed a method to estimate maximum propagation delay of 4-bit RCA, using only 44 input transitions (applied as primary-secondary and subsequently as secondary- primary). We applied our proposed method on 4-bit RCAs designed using seven different Full Adder (FA) circuits and simulated them in LTspice. The results from our proposed method (reduced input transitions) are compared with the results obtained by applying 261,632 input transitions (all possible transitions) to the 4-bit RCA. The simulation results prove that the maximum delay estimated by our proposed method is very close to the exact maximum delay of 4-bit RCA (found by applying ideal 261,632 input transitions), and has maximum 5.99% deviation.
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Mewada, M., Zaveri, M., Lakhlani, A. (2017). Estimating the Maximum Propagation Delay of 4-bit Ripple Carry Adder Using Reduced Input Transitions. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_2
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DOI: https://doi.org/10.1007/978-981-10-7470-7_2
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