Investigation of TCADs Models for Characterization of Sub 16 nm In$_{0.53}$Ga$_{0.47}$As FinFET

Abstract

At sub 16 nm In$_{0.53}$Ga$_{0.47}$As FinFET technology node the fabrication of device is quite complex in many sense. The study of such devices is only possible through TCAD simulations. To understand the behavior of such device the TCAD tool has to incorporate various simulation models related to physics of semiconductor and device geometry. In this paper, we have calibrated 50 nm In$_{0.53}$Ga$_{0.47}$As FinFET using various simulation models with experimental results and then same models are used to characterize $I_{d}-V_g$ and $I_{d}-V_{d}$ characteristics and along with the short channel parameters for the sub 16 nm In$_{0.53}$Ga$_{0.47}$As FinFET. The analysis is done on two types of devices i.e. Raised S/D with nitride spacers and without nitride spacers. Subthreshold slope SS (mV/dec) and DIBL (mV/V) for raised S/D In$_{0.53}$Ga$_{0.47}$As FinFET with spacers is measured as 65.48 and 38.4 respectively, while without spacers it is 84.45 and 44.