Abstract
PRESENT-80 algorithm is based on Substitution-Permutation Network (SPN) with a data-size of 64-bits and key-size of 80-bits. While the permutation operation can be performed by simple wiring, Substitution operation (S-box) is the only non-linear component consuming maximum resources. The existing works in literature concentrate on the algorithmic implementation of PRESENT. This work is the first of its kind to explore the circuit level implementation of PRESENT algorithm by identifying an optimized architecture for the S-box. This is achieved by realizing the PRESENT S-box using static CMOS logic styles in 180 nm technology. Comparison results of two different architectures of PRESENT S-box using the static CMOS logic styles is tabulated.
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Acknowledgement
This work has been done from the Grant Received from Visvesvaraya PhD Scheme for Electronics and IT. This work is also supported by SMDP-C2SD project sponsored by DeitY, Government of India.
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Shanthi Rekha, S., Saravanan, P. (2017). Low Cost Circuit Level Implementation of PRESENT-80 S-BOX. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_35
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DOI: https://doi.org/10.1007/978-981-10-7470-7_35
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