Abstract
Digital Adders and Multipliers are the backbone of Digital Signal Processing systems. A novel adder which uses Recursive Doubling technique for carry generation is propounded in this paper. A Multiplier based on Quarter square algorithm is designed and implemented using the proposed Cyclic Redundant Adder on Field Programmable Gate Array. The proposed Cyclic Redundant adder is compared amongst the recent high performance adders like Ling Adder, Carry Shifting Adder with carry increment and Carry Look Ahead Adder. The Cyclic Redundant adder has been observed to be the fastest with the least time delay of 2.719 ns for 64 bit input.
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Dheepika, K., Jevasankari, K.S., Chandhar, V., Kailath, B.J. (2017). Realization of Multiplier Using Delay Efficient Cyclic Redundant Adder. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_4
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DOI: https://doi.org/10.1007/978-981-10-7470-7_4
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