Abstract
The ever increasing demand to push the envelope for achieving superlative metrics of VLSI circuit performance along with denser logic packing and miniaturization of device dimensions, has rendered FPGAs to be more vulnerable to reliability hazards. This has led to reducing of the reliability and lifetime of VLSI chips. In this paper, we have proposed certain circuit techniques which comes along with the original design, to detect the presence of faulty FPGA logic slices, without significant compromise in performance. Primitive instantiation and constrained placement based approach was adopted for the circuit realizations to facilitate tracing of the exact faulty location, so that the faulty zones may be conveniently bypassed for fault-free circuit operation.
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Palchaudhuri, A., Dhar, A.S. (2017). Primitive Instantiation Based Fault Localization Circuitry for High Performance FPGA Designs. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_57
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DOI: https://doi.org/10.1007/978-981-10-7470-7_57
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