On Generation of Delay Test with Capture Power Safety

Abstract

Manufacturing test application without violation of circuit power budget is one of the primary concern for test engineers today. Excessive power demand often triggers false failures hence reduces the yield. Most of the automatic test pattern generation (ATPG) algorithms and test set modification methods have been proposed to minimize power requirement during the test. However, power reduction achieved is not enough as functional power budget of the circuit is usually much smaller than the high activity producing test patterns. This paper proposes an optimization problem formulation which targets test generation of transition delay faults without exceeding operative power limit. An optimization problem is constructed, and tests have been generated for slow-to-rise and slow-to-fall transition delay faults. The proposed method is capable of producing both Launch-On-Capture and Launch-On-Shift delay vectors. A pseudo SAT-based solver can be exercised to solve the formulated optimization problem. As the problem is optimized to maximize the number of faults detected under functional and power constraints of the circuit, this helps in generating the compact test set. Experiments are conducted on ISCAS89 benchmark circuits support the effectiveness of the proposed technique.