A Configurable and Area Efficient Technique for Implementing Isolation Cells in Low Power SoC

Abstract

In SoC design, isolation cells are used between different power domains to prevent the floating outputs/inputs of the power gated blocks from affecting the operations of the active circuits. At present, the low power SoCs use millions of isolation cells to implement different power gating modes and the isolation cells occupy considerable silicon area of the SoC. Also, the isolation values in low power designs are pre-determined (either fixed to ‘0’ or ‘1’ in design itself) and are non-configurable in real time operation. Hence, any incorrect isolation value may render the device useless in low power modes. In this paper, we propose a modified clamping circuit design to reduce the area and delay of the isolation cells. We also propose a method to configure the isolation values for certain qualifier signals and the subsequent entry process of the power gated modules into deep-sleep mode. The results show that the proposed technique can improve reliability of the power gating modes and reduce 30% to 50% of isolation cell area compared to that of the conventional isolation technique using logic gates.