Abstract
In this paper, a PVT compensated, 10 MHz oscillator in 0.11 µm BCD9S (Bipolar CMOS DMOS) technology for embedded phase change memories (PCM) is reported. The proposed oscillator produces a frequency deviation of ±0.4% for typical corner, ±2% for slow corner and ±1.5% for fast corner around 10 MHz across −40 °C to 150 °C at a regulated supply of 1.8 V. It is a significant advancement in the existing state-of-the-art for frequency references.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Bedeschi, F., et al.: 4-Mb MOSFET-selected phase-change memory experimental chip. In: Proceedings of the 30th European Solid-State Circuits Conference, pp. 207–210 (2004)
Sundaresan, K., Allen, P., Ayazi, F.: Process and temperature compensation in a 7-MHz CMOS clock oscillator. IEEE J. Solid-State Circuits 41(2), 433–442 (2006)
Sadeghi, N., Bakhtiar, A.S., Mirabbasi, S.: A 0.007 mm2 108-ppm/°C 1-MHz relaxation oscillator for high-temperature applications up to 180 °C in 0.13 μm CMOS. IEEE Trans. Circuits Syst. I, Reg. Papers 60(7), 1692–1701 (2013)
Sebastiano, F., Nauta, B., et al.: A 65-nm CMOS temperature compensated mobility-based frequency reference for wireless sensor networks. In: Proceedings of the ESSCIRCs, pp. 102–105, September 2010
Lee, J., Cho, S.: A 10 MHz 80 μW 67 ppm/°C CMOS reference clock oscillator with a temperature compensated feedback loop in 180 nm CMOS. In: Proceedings of the VLSI, pp. 226–227, June 2009
Ueno, K., Asai, T., Amemiya, Y.: A 30 MHz, 90-ppm/°C fully integrated clock reference generator with frequency-locked loop. In: Proceedings of the ESSCIRCs, pp. 392–395, September 2009
Tokunaga, Y., Saki Yama, S., Matsumoto, A., Dosho, S.: An on-chip CMOS relaxation oscillator with voltage averaging feedback. IEEE J. Solid-State Circuits 45, 1150–1158 (2010)
Milliken, R.J., Silva-Martinez, J., Sanchez-Sinencio, E.: Full on-chip CMOS low-dropout voltage regulator. IEEE Trans. Circuits Syst. I: Regular Papers 54(9), 1879–1890 (2007)
Wolpert, D., Ampadu, P.: Managing Temperature Effects in Nanoscale Adaptive Systems. Springer, New York (2012)
Chil, M.N., et al.: Advanced 300 mm 130 nm BCD technology from 5 V to 85 V with Deep-Trench Isolation. In: 2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Prague, pp. 403–406 (2016)
Sengupta, S., Saurabh, K., Allen, P.E.: A process, voltage, and temperature compensated CMOS constant current reference. In: 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No. 04CH37512), vol. 1, pp. I-325–I-328 (2004)
Wang, D., Tan, X.L., Chan, P.K.: A 65-nm CMOS constant current source with reduced PVT variation. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(4), 1373–1385 (2017)
Acknowledgements
The authors would like to thanks the Smart-power Technology group at ST Microelectronics, India for providing CAD Tools as well as technical support throughout the work.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2017 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Tyagi, V., Hashmi, M.S., Raj, G., Rana, V. (2017). A 10 MHz, 42 ppm/\( ^{ \circ } {\text{C}} \), 69 μW PVT Compensated Latch Based Oscillator in BCD9S Technology for PCM. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_60
Download citation
DOI: https://doi.org/10.1007/978-981-10-7470-7_60
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-7469-1
Online ISBN: 978-981-10-7470-7
eBook Packages: Computer ScienceComputer Science (R0)