A 1.8 V Gain Enhanced Fully Differential Doubly-Recycled Cascode OTA with 100 dB Gain 200 MHz UGB in CMOS

Abstract

A fully differential OTA based on modified Doubly Recycling current technique is presented here. The proposed technique uses a Gm boosted Cascode stage at the output, there by enhancing the DC gain of recycling cascode OTA with an improved phase margin. 102 dB of DC gain is achieved, which is almost 20 dB more than the existing architectures designed at 1.8 V supply. Enhancement of gain helps in reducing the input referred noise down to 10 uV/$\mathrm{{\sqrt{Hz}}}$. The designed OTA achieves UGB of 200 MHz at a capacitive load of 10 pF which makes it suitable for high speed applications. The OTA is designed in standard 45 nm CMOS Process. The 2 stage OTA uses MCNR approach to emulate first order Phase response before UGB, giving a Phase Margin of more than 69$^{\circ }$ for typical load of 10 pF. The input referred noise is 10 $\upmu$V/$\mathrm{{\sqrt{Hz}}}$ at 10 Hz and Slew Rate 105 V/$\upmu$S for load of 1 pF.