Abstract
In spite of state explosion problem in the present era of complex and large designs, formal methods have been utilized for pre-silicon verification with limited success. This paper critically analyzes some of the reported work on usage of formal principles for effective root-cause finding of bugs during post-silicon validation and debugging. The application of trace buffers assist in mitigating the problem of limited observability of internal states during debug at post-silicon stage. This paper proposes the usage of state restoration principle to increase the efficiency of the formal methods of post-silicon debugging. To solve the problem of trace signal selection, a methodology based on formal principles is presented to increase the effectiveness of trace signals.
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Kumar, B., Basu, K., Jindal, A., Pandey, B., Fujita, M. (2017). A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_71
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DOI: https://doi.org/10.1007/978-981-10-7470-7_71
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