Abstract
This paper describes the hardware design of 4 × 4 block-based Sample Adaptive Offset (SAO) for high-performance HEVC. The HEVC in-loop filter consists of a deblocking filter and SAO. SAO is used to compensate for errors in image compression. However, it has a high latency due to pixel-based computation. The proposed hardware architecture performs 4 × 4 block-based operations and has high throughput through a two-stage pipeline. The offset operation module minimizes the hardware area by using the adder and the right shift operations. The proposed hardware architecture is synthesized using a 65 nm cell library. The maximum operating frequency is 312.5 MHz and the total number of gates is 193.6 k.
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Acknowledgements
This research was supported by the MSI (Ministry of Science, ICT and Future Planning), Korea, under the Global IT Talent support program (IITP-2017-0-01681) and Human Resource Development Project for Brain scouting program (IITP-2016-0-00352) supervised by the IITP (Institute for Information and Communication Technology Promotion).
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Park, S., Ryoo, K. (2019). Hardware Design of HEVC In-Loop Filter for Ultra-HD Video Encoding. In: Park, J., Loia, V., Choo, KK., Yi, G. (eds) Advanced Multimedia and Ubiquitous Engineering. MUE FutureTech 2018 2018. Lecture Notes in Electrical Engineering, vol 518. Springer, Singapore. https://doi.org/10.1007/978-981-13-1328-8_52
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DOI: https://doi.org/10.1007/978-981-13-1328-8_52
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