Abstract
The study of Hardware Trojan and its impact is a cutting edge research topic today. Hardware Trojan Horses (HTH) are inserted by an adversary either during design or fabrication phase of IC which does the malicious alterations in the circuit. The main objective of this paper is to insert two new hardware Trojan designs on cryptosystem and study its impact by calculating path delay, power consumption and area utilization. In particular, the proposed Trojan is designed using single trigger with multiple payloads structure. These designs are imposed to do the malicious action of fault injection on the penultimate mixcolumn of AES-128, which enables to extract the entire 128 bit secret key with minimum time of activation on the HTHs by performing Differential Fault Analysis (DFA). Both the Trojan inserted AES designs are implemented on the Xilinx Virtex-5 FPGAs. The proposed Trojan designs, HT1 and HT2 have minimal area overhead of 0.7% and 1.5% respectively with frequency overhead of 2% each. Provided, the models designed have a negligible effect on path delay and power consumption when compared to the original AES.
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Manivannan, S., Nalla Anandakumar, N., Nirmala Devi, M. (2019). Key Retrieval from AES Architecture Through Hardware Trojan Horse. In: Thampi, S., Madria, S., Wang, G., Rawat, D., Alcaraz Calero, J. (eds) Security in Computing and Communications. SSCC 2018. Communications in Computer and Information Science, vol 969. Springer, Singapore. https://doi.org/10.1007/978-981-13-5826-5_37
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