Abstract
To improve the performance of the GPU, more parallelism should be exploited and the GPU should be operated at higher clock frequency. However, high parallelism and high clock frequency cause serious memory contention problems, resulting in significant power consumption and increased idle cycles in the GPU. This paper proposes a new memory contention aware (MC-aware) power management scheme to reduce the power consumption of the GPU with little impact on the performance. When serious memory contention problems occur in the GPU, the proposed MC-aware scheme changes the mode of the SM (Streaming Multiprocessor) to power saving mode with little performance degradation. The proposed scheme monitors the degree of memory contention, since severe memory contention causes serious performance degradation. The proposed GPU architecture includes SM management unit that generates the control signals based on the estimated degree of memory contention. According to our simulation results, the proposed MC-aware scheme can increase the power efficiency, IPC per watt, by up to 31.4% compared to the conventional architecture.
This study was financially supported by Chonnam National University. (Grant number: 2017-2727).
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Luebke, D., Humphreys, G.: How GPUs work. J. Comput. 40, 96–100 (2007)
Buck, I., et al.: Brook for GPUs: stream computing on graphics hardware. ACM Trans. Graph. 23, 777–786 (2004)
General-purpose computation on graphics hardware. http://www.gpgpu.org/
GTX480 NVIDIA. http://www.geforce.com/hardware/desktop-gpus/geforce-gtx-480
Jing, N., et al.: An energy-efficient and scalable eDRAM-Based register file architecture for GPGPU. ACM SIGARCH Comput. Arch. News 41, 344–355 (2013)
Rhu, M., Erez, M.: The dual-path execution model for efficient GPU Control Flow. In: High Performance Computer Architecture, pp. 591–602 (2013)
Gilani, S.Z., Kim, N.S., Schulte, M.J.: Power-efficient computing for compute-intensive GPGPU applications. In: High Performance Computer Architecture, pp. 330–341 (2013)
Fung, W.W.L., Sham, I., Yuan, G., Aamodt, T.M.: Dynamic warp formation and scheduling for efficient GPU Control Flow. In: Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 407–420 (2007)
Thornton, J.E.: Parallel operation in the control data 6600. In: Fall Joint Computer Conference, Part II: Very High Speed Computer Systems, AMC (1964)
CUDA Programming Guide Version 3.0. https://developer.nvidia.com/cuda-toolkit-30-downloads/
Abdalla, K.M., et al.: US Patent US20130185725: Scheduling and Execution of Compute Tasks (2013)
Abdel-Majeed, M., et al.: Gating aware scheduling and power gating for GPGPUs. In: Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 111–122 (2013)
Wang, P.-H., Yang, C.-L., Chen, Y.-M., Cheng, Y.-J.: Power gating strategies on GPUs. ACM Trans. Arch. Code Optim., 8, (2011)
Leng, J., et al.: GPUWattch: enabling energy optimizations in GPGPUs. In: Proceedings of the International Symposium Computer Architecture, pp. 487–498 (2013)
Bakhoda, A., Yuan, G.L., Fung, W.W.L., Wong, H., Aamodt, T.M.: Analyzing CUDA workloads using a detailed GPU simulator. In: Performance Analysis of Systems and Software, pp. 163–174 (2009)
Li, S., Ahn, J.H., Strong, R.D., Brockman, J.B., Tullsen, D.M., Jouppi, N.P.: McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures. In: Microarchitecture MICRO-42, pp. 469–480 (2009)
SDK CUDA SDK. http://developer.download.nvidia.com/compute/cuda/sdk/
Goodrum, M.A., Trotter, M.J., Aksel, A., Acton, S.T., Skadron, K.: Parallelization of particle filter algorithms. In: Varbanescu, A.L., Molnos, A., van Nieuwpoort, R. (eds.) ISCA 2010. LNCS, vol. 6161, pp. 139–149. Springer, Heidelberg (2011). https://doi.org/10.1007/978-3-642-24322-6_12
Acknowledgements
This study was financially supported by Chonnam National University (Grant number: 2017-2727).
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Choi, H.J., Son, D.O., Kim, C.H. (2019). Memory Contention Aware Power Management for High Performance GPUs. In: Park, J., Shen, H., Sung, Y., Tian, H. (eds) Parallel and Distributed Computing, Applications and Technologies. PDCAT 2018. Communications in Computer and Information Science, vol 931. Springer, Singapore. https://doi.org/10.1007/978-981-13-5907-1_23
Download citation
DOI: https://doi.org/10.1007/978-981-13-5907-1_23
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-13-5906-4
Online ISBN: 978-981-13-5907-1
eBook Packages: Computer ScienceComputer Science (R0)