Abstract
Globalization of the modern semiconductor design industry has evicted the hardware root of trust. Security principles are compromised at runtime due to the implantation of malicious circuitry or Hardware Trojan Horse (HTH) in the vulnerable stages of System on Chip (SoC) design, from less trusted third parties. Runtime security from integrity attacks or erroneous result generation due to HTHs is the focus of this work. The prevailing techniques adopt a redundancy based approach. Several limitations are associated with the redundancy based approach like inability to perform multitasking in a multitasking environment, inability to adapt to aging, use of fault diagnosis even in normal scenario and severe overhead in area and power. Incorporation of observe, decide and act (ODA) paradigm in the design of a SoC makes it self aware. We propose a self aware approach for facilitating runtime security, which overcomes the limitations of the existing redundancy based approach. Low overhead in area and power and better throughput than the redundancy based approaches as observed in experimental results aid its application for practical scenarios.
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Acknowledgement
This work is sponsored by the Department of Science and Technology, Government of India, INSPIRE Fellowship Number: 150916.
This research is supported by TEQIP Phase III, University of Calcutta (UCT-CU).
This work has also been supported partially through resources and financially by SMDP-C2SD project of the University of Calcutta, funded by MeitY, Government of India.
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Guha, K., Saha, D., Chakrabarti, A. (2019). SARP: Self Aware Runtime Protection Against Integrity Attacks of Hardware Trojans. In: Rajaram, S., Balamurugan, N., Gracia Nirmala Rani, D., Singh, V. (eds) VLSI Design and Test. VDAT 2018. Communications in Computer and Information Science, vol 892. Springer, Singapore. https://doi.org/10.1007/978-981-13-5950-7_17
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