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A Novel Countermeasure Against Differential Scan Attack in AES Algorithm

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VLSI Design and Test (VDAT 2018)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 892))

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Abstract

The Design for Testability (specifically scan designs) is standard testing techniques for Digital cores for achieving high fault coverage and to provide better controllability and observability. However, such test architectures in the chip containing secret data mostly becomes the instrumental for secret information leakage. The attacker may use different implementation attacks to leak the secret data. In this paper, we first analyse the existing scan designs from security perspective. We demonstrated that how the secret key is retrieved by differential scan attack (DSA) in case of symmetric encryption standards (AES). Furthermore, it is also shown that AES along with time compactor also fails to provide sufficient security. We then propose novel prevention mechanism, Modular Exponentiation Secure Scheme (ME-SS), which clears the insecure states of all the existing techniques. Our experimental results show that the proposed countermeasures can effectively insulate all the information related to cipher key from DSA.

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Acknowledgment

We are thankful to Research Progress Committee members Dr. K.S. Dasgupta and Dr. Virendra Singh for their review, insightful comments and constructive suggestions.

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Authors and Affiliations

  1. Institute of Technology, Nirma University, Ahmedabad, Gujrat, India

    Jayesh Popat & Usha Mehta

Authors
  1. Jayesh Popat
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  2. Usha Mehta
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Corresponding author

Correspondence to Jayesh Popat .

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Editors and Affiliations

  1. Thiagarajar College of Engineering, Madurai, India

    S. Rajaram

  2. Thiagarajar College of Engineering, Madurai, India

    N.B. Balamurugan

  3. Thiagarajar College of Engineering, Madurai, India

    D. Gracia Nirmala Rani

  4. Indian Institute of Technology Bombay, Mumbai, India

    Virendra Singh

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Popat, J., Mehta, U. (2019). A Novel Countermeasure Against Differential Scan Attack in AES Algorithm. In: Rajaram, S., Balamurugan, N., Gracia Nirmala Rani, D., Singh, V. (eds) VLSI Design and Test. VDAT 2018. Communications in Computer and Information Science, vol 892. Springer, Singapore. https://doi.org/10.1007/978-981-13-5950-7_26

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  • DOI: https://doi.org/10.1007/978-981-13-5950-7_26

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-13-5949-1

  • Online ISBN: 978-981-13-5950-7

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