Abstract
Convolutional Neural Networks (CNN) are biologically inspired architectures which can be trained to perform various classification tasks. CNNs typically consists of convolutional layers, max pooling layers, followed by dense fully connected layers. Convolutional layer is the compute intensive layer in CNNs. In this paper we present FFT (Fast Fourier Transform) based convolution technique for accelerating CNN architecture. Computational complexity of direct convolution and FFT convolution are evaluated and compared. Also we present an efficient FFT architecture based on radix-4 butterfly for convolution. For validating our analysis we have implemented a convolutional layer in Virtex-7 FPGA.
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Kala, S., Jose, B.R., Paul, D., Mathew, J. (2019). A Hardware Accelerator for Convolutional Neural Network Using Fast Fourier Transform. In: Rajaram, S., Balamurugan, N., Gracia Nirmala Rani, D., Singh, V. (eds) VLSI Design and Test. VDAT 2018. Communications in Computer and Information Science, vol 892. Springer, Singapore. https://doi.org/10.1007/978-981-13-5950-7_3
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DOI: https://doi.org/10.1007/978-981-13-5950-7_3
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