Abstract
The continuous advancements in the Network on Chip technology emphasizes the need for fault tolerant designs. In this work, we propose a routing technique that handles multiple link faults. We use flit parameters to handle the fault in the routing path. Experimental analysis show that the proposed routing technique is capable of routing packets even with two fault locations and the packets are received in the destination router without any error. In addition, hardware implementation done using ZedBoard Zynq FPGA hardware kit shows that our design is having minor area overhead compared to the standard XY routing and it’s a significantly better choice than the other fault tolerant algorithms.
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Acknowledgement
This work is supported in part by a grant from DST Government of India, SERB-ECR scheme (project number ECR/2016/212)
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B. P., A. et al. (2019). Implementation of a Novel Fault Tolerant Routing Technique for Mesh Network on Chip. In: Rajaram, S., Balamurugan, N., Gracia Nirmala Rani, D., Singh, V. (eds) VLSI Design and Test. VDAT 2018. Communications in Computer and Information Science, vol 892. Springer, Singapore. https://doi.org/10.1007/978-981-13-5950-7_42
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DOI: https://doi.org/10.1007/978-981-13-5950-7_42
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