Abstract
Network-on-Chip helps to accomplish greater throughput in multi-core chips. In a multi-core chip, each core parallelly processes multiple applications thereby increasing the overall processing capability of the chip. One of the major concern in this field is managing congestion on the network. There are many reasons for congestion, one of them is hotspots, which has been considered in this paper. The applications on a multi-core architecture that operates on large amount of data and computation may create hotspots. These hotspots introduce congestion on the network and increase the latency of packets that pass through them. Our solution to hotspots, identify the source hotspots and decrease inflow of packets into the hotspots, thereby reducing the network pressure where hotspots are present. The congestion control scheme is a threshold based approach that dynamically evaluates the presence of hotspots on the network and a routing algorithm to effectively route the packets away from the hotspots. Our experimental results show that the packets are routed away from the source hotspots and the packet latency of the network is effectively reduced.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Wang, C., Hu, W., Bagherzadeh, N.: Scalable load balancing congestion-aware network-on-chip router architecture. J. Comput. Syst. Sci. 79(4), 421–439 (2013)
Reshma Raj, R.S., Das, A., Jose, J.: Implementation and analysis of hotspot mitigation in mesh NoCs by cost-effective deflection routing technique. In: IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Abu Dhabi, pp. 1–6 (2017)
Link, G.M., Vijaykrishnan, N.: Hotspot prevention through runtime reconfiguration in network-on-chip. In: Design, Automation and Test in Europe (DATE), pp. 648–649 (2005)
Huang, W., et al.: HotSpot: a compact thermal modeling methodology for early-stage VLSI design. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 14(5), 501–513 (2006)
Gindin, R., et al.: NoC-based FPGA: architecture and routing. In: International Symposium on Networks-on-Chip (NOCS), pp. 253–264 (2007)
Kakoulli, E., et al.: HPRA: a pro-active hotspot-preventive high-performance routing algorithm for networks-on-chips. In: International Conference on Computer Design (ICCD), pp. 249–255 (2012)
Kakoulli, E., et al.: Intelligent hotspot prediction for network-on-chip based multicore systems. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 31(3), 418–431 (2012)
Gupte, A., Jones, P.: Hotspot mitigation using dynamic partial reconfiguration for improved performance. In: International Conference on Reconfigurable Computing and FPGAs (ReConFig), pp. 89–94 (2009)
Alfaraj, N., et al.: HOPE: hotspot congestion control for Clos network on chip. In: International Symposium on Networks-on-Chip (NOCS), pp. 17–24 (2011)
Tang, M., Lin, X., Palesi, M.: The repetitive turn model for adaptive routing. IEEE Trans. Comput. 66(1), 138–146 (2017)
Tsai, W.-C., Chu, K.-C., Hu, Y.-H., Chen, S.-J.: Non-minimal, turn-model based NoC routing. Microprocess. Microsyst. 37(8, Part B), 899–914 (2013). ISSN 0141–9331
Benini, L., De Micheli, G.: Networks on chips: a new SoC paradigm. Computer 35, 70–78 (2002)
Tatas, K., Siozios, K., Soudris, D., Jantsch, A.: Designing 2D and 3D Network on-Chip Architectures, 1st edn, p. 265. Springer, New York (2014). https://doi.org/10.1007/978-1-4614-4274-5
Jiang, N., et al.: A detailed and flexible cycle-accurate network-on-chip simulator. In: International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 86–96 (2013)
Binkert, N., et al.: The gem5 simulator. ACM SIGARCH Comput. Arch. News 39(2), 1 (2011)
Zedboard.org Zedboard. http://www.zedboard.org/product/zedboard
Xilinx.com Xilinx. http://www.xilinx.com/products/design-tools/vivado
Acknowledgement
This work is supported in part by a grant from DST Government of India, SERB-ECR scheme (project number ECR/2016/212).
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
S, A. et al. (2019). Source Hotspot Management in a Mesh Network on Chip. In: Rajaram, S., Balamurugan, N., Gracia Nirmala Rani, D., Singh, V. (eds) VLSI Design and Test. VDAT 2018. Communications in Computer and Information Science, vol 892. Springer, Singapore. https://doi.org/10.1007/978-981-13-5950-7_51
Download citation
DOI: https://doi.org/10.1007/978-981-13-5950-7_51
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-13-5949-1
Online ISBN: 978-981-13-5950-7
eBook Packages: Computer ScienceComputer Science (R0)