A Comparative Exploration About Approximate Full Adders for Error Tolerant Applications

Abstract

Arithmetic units such as adders and multipliers play an essential role in the performance of Digital signal processor (DSP) systems. The efficiency of the Processors are influenced by the speed and power consumption of arithmetic units. It is improved by adopting approximate computing in arithmetic units with acceptable degradation in the output. Approximate computing is an emerging topic in the past decades, it aims to achieve promising design approach with the sacrifices in computational quality for error resilient applications. Approximate computing can be adopted both in hardware level and software level of research. This paper provides an elaborative investigation about approximate computing on full adders which is explored at the hardware level. The approximation is applied to full adders either at gate level or transistor level. Further, ripple carry adder is designed for varying bit width with different degrees of approximation using these approximate Full adders. Ripple carry adder is estimated based on the structural analysis such as Area, Delay Product (ADP) and Power, Delay Product (PDP) and error matrix such as pass rate, error rate, Normalized Error Distance (NED) and Mean Error Distance (MED). The ripple carry adders are designed in Verilog HDL and stimulated in Synopsys Design Compiler (DC) using tsmc 65 nm standard cell library typical corner whereas, the error characteristics is done in MATLAB.

Supported by organization VIT.