Abstract
In this paper, two one-bit full adder design techniques are explored for reduced power consumption in standby mode. The proposed algorithm based techniques compute optimal transistor sizing for variable operating conditions (temperature, supply voltage) to achieve desirable leakage power and speed for a full-adder circuit. Both techniques use ‘SLEEP’ signal to drive full adder circuit to lower standby mode leakage state without even degrading the performances in active mode. The investigation has been carried out for 45 nm, 32 nm, 22 nm Metal Gate High-K PTM models and all the simulation characterizations are carried out using HSPICE simulation tool. Performance comparison of both techniques after optimization has been done over a complete range temperature (−40 \(^\circ \)C−125 \(^\circ \)C) and ±5% variation in supply voltage. The resultant designs are tested on large full-adder based digital circuits to analyze the reduced standby leakage power. The results show that up to 97% of standby leakage reduction can be obtained with (0.4–15)% delay overhead using the proposed methods of full-adder design.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Deepaksubramanyan, B.S., Nunez, A.: Analysis of subthreshold leakage reduction in CMOS digital circuits. In: 2007 50th Midwest Symposium on in Circuits and Systems, MWSCAS 2007, pp. 1400–1404 (2007)
Abbas, Z., Olivieri, M.: Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells. Microelectron. J. 45(2), 179–195 (2014)
Lee, B.H., Song, S.C., Choi, R., Kirsch, P.: Metal electrode/high-\( k \) dielectric gate-stack technology for power management. IEEE Trans. Electron Devices 55(1), 8–20 (2008)
Mukhopadhyay, S., Neau, C., Cakici, R.T., Agarwal, A., Kim, C.H., Roy, K.: Gate leakage reduction for scaled devices using transistor stacking. IEEE Trans. Very Large Scale Integr. Syst. 11(4), 716–730 (2003)
Abdollahi, A., Fallah, F., Pedram, M.: Leakage current reduction in CMOS VLSI circuits by input vector control. IEEE Trans. Very Large Scale Integr. Syst. 12(2), 140–154 (2004)
Roy, K., Mukhopadhyay, S., Mahmoodi-Meimand, H.: Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. IEEE 91(2), 305–327 (2003)
Singh, H., Agarwal, K., Sylvester, D., Nowka, K.J.: Enhanced leakage reduction techniques using intermediate strength power gating. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 15(11), 1215–1224 (2007)
Chinta, V., Kudithipudi, D.: Minimum leakage vector pattern estimation. In: 2007 50th Midwest Symposium on Circuits and Systems, MWSCAS 2007, pp. 1066–1069. IEEE (2007)
Singh, A., Gulati, K., Khatri, S.P.: Minimum leakage vector computation using weighted partial MaxSAT. In: 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 201–204. IEEE (2010)
Yuan, L., Qu, G.: A combined gate replacement and input vector control approach for leakage current reduction. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 14(2), 173–182 (2006)
Fallah, F., Pedram, M.: Standby and active leakage current control and minimization in CMOS VLSI circuits. IEICE Trans. Electr. 88(4), 509–519 (2005)
Alioto, M., Palumbo, G.: Analysis and comparison on full adder block in submicron technology. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 10(6), 806–823 (2002)
Abbas, Z., Olivieri, M.: Optimal transistor sizing for maximum yield invariation-aware standard cell design. Int. J. Circ. Theory Appl. 44(7), 1400–1424 (2016)
Abbas, Z., Mastrandrea, A., Olivieri, M.: A voltage-based leakage current calculation scheme and its application to nanoscale mosfet and finfet standard-cell designs. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(12), 2549–2560 (2014)
Man, K.-F., Tang, K.-S., Kwong, S.: Genetic algorithms: concepts and applications [in engineering design]. IEEE Trans. Ind. Electr. 43(5), 519–534 (1996)
Xue, B., Zhang, M., Browne, W.N., Yao, X.: A survey on evolutionary computation approaches to feature selection. IEEE Trans. Evol. Comput. 20(4), 606–626 (2016)
Eberhart, R., Kennedy, J.: A new optimizer using particle swarm theory. In: 1995 Proceedings of the Sixth International Symposium on Micro Machine and Human Science, MHS 1995, pp. 39–43. IEEE (1995)
Arasomwan, M.A., Adewumi, A.O.: Improved particle swarm optimization with a collective local unimodal search for continuous optimization problems. Sci. World J. 2014 (2014)
Weste, N.H., Harris, D.: CMOS VLSI Design: A Circuits and Systems Perspective. Pearson Education India, New Delhi (2015)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Gupta, P., Kumar, S., Abbas, Z. (2019). Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Power. In: Rajaram, S., Balamurugan, N., Gracia Nirmala Rani, D., Singh, V. (eds) VLSI Design and Test. VDAT 2018. Communications in Computer and Information Science, vol 892. Springer, Singapore. https://doi.org/10.1007/978-981-13-5950-7_8
Download citation
DOI: https://doi.org/10.1007/978-981-13-5950-7_8
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-13-5949-1
Online ISBN: 978-981-13-5950-7
eBook Packages: Computer ScienceComputer Science (R0)