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Improvement in Fault Clearance Time of the Cascaded H-Bridge Multilevel Inverter Using Novel Technique Based on Frequency Detection

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Modeling, Simulation and Optimization

Part of the book series: Smart Innovation, Systems and Technologies ((SIST,volume 206))

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Abstract

In this paper, a novel frequency detection technique has been proposed for five-level cascaded H-bridge multilevel inverter (CHBI) to improve the fault clearance time. The open circuit and short circuit fault of semiconductor switches have been diagnosed and cleared by measuring the PWM frequency of different levels of output voltage. The variable frequency sinusoidal frequency pulse width modulation (VFSPWM) has been adopted to generate a different frequency of each level in the output voltage. The simulation of the VFSPWM technique for CHBI, frequency detection technique and the effect of open circuit and short circuit switches has been performed using MATLAB/Simulink. Further, the fault clearance time has been analyzed by incorporating the open circuit and short circuit fault. The fault clearance time has been compared with that of existing results presented in the previous research papers.

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Correspondence to Jiwanjot Singh .

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Phukan, H., Singh, J. (2021). Improvement in Fault Clearance Time of the Cascaded H-Bridge Multilevel Inverter Using Novel Technique Based on Frequency Detection. In: Das, B., Patgiri, R., Bandyopadhyay, S., Balas, V.E. (eds) Modeling, Simulation and Optimization. Smart Innovation, Systems and Technologies, vol 206. Springer, Singapore. https://doi.org/10.1007/978-981-15-9829-6_38

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