Abstract
New Number Field Sieves (NFS) attacks on the discrete logarithm problem have led to increasing the key size of pairing-based cryptography on most popular curves like BN. To ensure 128-bit security level, recent cost estimations between several pairing friendly elliptic curves recommend to switch for BLS24 curves. However, implementing a pairing on a BLS24 curve requires arithmetic operation over \(\mathbb {F}_{p^4}\). In this paper, we transpose previous work on multiplication over extension fields using Newton’s interpolation to construct a new formula for multiplication in \(\mathbb {F}_{p^4}\) and propose efficient hardware implementation of this operation. Our Arithmetic Logic Unit (ALU) is implemented on Kintex-7 Xilinx\(^{\text{\textregistered }}\) FPGA. The efficiency of our design in terms of \(\boldsymbol{time\times area}\) is almost 3 times better than previous specific architectures for multiplication in \(\mathbb {F}_{p^4}\). We also used this new architecture to estimate full pairing implementations on BLS24 and KSS16 for 128 and 192-bit security level. These estimations highlight that the new \(\mathbb {F}_{p^4}\) formula allows a performance increase between 5 and 10%. And especially for KSS16 which appears to provide the best performance at the 128-bit level.
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Lavice, A., El Mrabet, N., Berzati, A., Rigaud, JB. (2022). Hardware Implementation of Multiplication over Quartic Extension Fields. In: Giri, D., Raymond Choo, KK., Ponnusamy, S., Meng, W., Akleylek, S., Prasad Maity, S. (eds) Proceedings of the Seventh International Conference on Mathematics and Computing . Advances in Intelligent Systems and Computing, vol 1412. Springer, Singapore. https://doi.org/10.1007/978-981-16-6890-6_43
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DOI: https://doi.org/10.1007/978-981-16-6890-6_43
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