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An On-Chip Integrated CMOS Ring Mixer-Balun-VCO Achieving IIP3 of 11.2 dBm and Phase Noise of −117.2 dBc/Hz

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Proceedings of the 11th International Conference on Robotics, Vision, Signal Processing and Power Applications

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 829))

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Abstract

This paper presents an integrated up-conversion passive mixer fitted with an on chip active RF Balun merged with Class-C VCO. This combo architecture limit the use of off chip passive balun for combining the differential signal input to single-ended signal output implemented in RF Transmitter system. The proposed architecture adopts a symmetric passive ring mixer for high linearity, port to port isolation and stable matching. The mixer achieves highest power conversion gain of 36 dB across the VCO input power, high input 3rd order intercept point (IIP3) of 11.2 dBm and gain of 8 dB at 2.45 GHz. The integrated VCO results in phase noise of −117.2 dBc/Hz at 1 MHz offset with large signal output power of 5.2 dBm. The entire architecture occupies chip area of 1.21 mm2 designed in 180 nm technology, consuming 5 mW of dc power consumption under supply voltage of 1 V.

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Acknowledgement

This work is supported by CREST grant number PCEDEC/6050415, MOHE FRGS grant number PCEDEC/6071449, USM RUI grant 1001/PCEDEC/8014079 and Silterra Malaysia for CMOS 180 nm fabrication support.

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Correspondence to Jagadheswaran Rajendran .

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Shasidharan, P., Rajendran, J., Mariappan, S., Yusof, Y.M. (2022). An On-Chip Integrated CMOS Ring Mixer-Balun-VCO Achieving IIP3 of 11.2 dBm and Phase Noise of −117.2 dBc/Hz. In: Mahyuddin, N.M., Mat Noor, N.R., Mat Sakim, H.A. (eds) Proceedings of the 11th International Conference on Robotics, Vision, Signal Processing and Power Applications. Lecture Notes in Electrical Engineering, vol 829. Springer, Singapore. https://doi.org/10.1007/978-981-16-8129-5_100

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