Skip to main content
Springer Nature Link
Log in

Speeding Parasitic-Extraction Stage in Layout-Change-Order Validation Cycle Through Net-Tracing and Layout Trimming

  • Conference paper
  • First Online:
Proceedings of the 11th International Conference on Robotics, Vision, Signal Processing and Power Applications

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 829))

  • 1866 Accesses

Abstract

A real layout design cutting solution to speed up the post-layout extraction run time is presented. It reduced the extraction run time down to less than 10 min for a huge design block with Electrical Changes Order (ECO) consist of small layout area changes and able to maintain the accuracy within 1%. The solution can be applied to improve the In-Die-Variation (IDV), System-On-chip (SoC) level Electrical Static Discharge (ESD) structure verification and 3D-IC interface verification without accuracy loss with runtime and memory consumption reduction.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Similar content being viewed by others

References

  1. Lescot, J., Dehan, P., Boujarra, W., Medhat, D., Billy, S.: A comprehensive ESD verification flow at transistor level for large SoC designs. In: 2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), pp. 1–6 (2015)

    Google Scholar 

  2. Mutschler, A.S.: The problem with post-silicon debug, 28 February 2019. https://semiengineering.com/the-problem-with-post-silicon-debug/. Accessed 15 Nov 2020

  3. Miller, G., Bhattarai, B., Hsu, Y.C., Dutt, J., Chen, X., Bakewell, G.: A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation. In: 48th ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 575–578, 2011

    Google Scholar 

  4. Qian, K.: Thesis: Variability Modeling and Statistical Parameter Extraction for CMOS Devices. University of California, Berkeley (2015)

    Google Scholar 

  5. Dusan Petranovic, K.C.: 3D-IC system verification methodology: solutions and challenges. In: Electronic Design Process Symposium, Monterey, California (2011)

    Google Scholar 

  6. Jain, B.: A comparative study of methodologies to optimize post-layout challenges. Int. J. Comput. Appl. (0975 – 8887) 124(8), 27–30 (2015)

    Google Scholar 

  7. SynopSys: Smarter and faster galaxy incremental ECO (2017). https://www.synopsys.com/news/pubs/snug/2017/france/c3-02-thaller-pres-snps.pdf. Accessed 23 Nov 2020

  8. SynopSys: The StarRC Incremental ECO Flow (2020). https://spdocs.synopsys.com/dow_retrieve/R-2020.09/dg/starolh/Default.htm#stug/stug/eco_extraction/starrc_incremental_eco_flow.htm. Accessed 23 Nov 2020

  9. Benk, J., Denk, G., Waldherr, K.: A holistic fast and parallel approach for accurate transient simulations of analog circuits. J. Math. Ind. 7(1), 1–19 (2017). https://doi.org/10.1186/s13362-017-0042-z

    Article  MathSciNet  MATH  Google Scholar 

  10. Yi, Y., Yan, S., Sarin, V., Shi, W.: Development of fast 3D parasitic extraction using hierarchical method for integrated circuits and packages. In: 2008 IEEE Antennas and Propagation Society International Symposium, pp. 1–4 (2008)

    Google Scholar 

  11. Bachtold, M., Spasojevic, M., Lage, C., Ljung, P.B.: A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19, 25–338 (2000)

    Article  Google Scholar 

  12. SynopSys: Extraction techniques for high-performance, high-capacity simulation, September 2009. https://www.synopsys.com/content/dam/synopsys/verification/white-papers/extraction_tech_wp.pdf. Accessed 23 Nov 2020

Download references

Acknowledgment

We would like to thank Collaborative Microelectronic Design Excellence Center (CEDEC) for the tools and collaterals setup to enable the development works.

Author information

Authors and Affiliations

  1. School of Electrical and Electronic Engineering, Universiti Sains Malaysia, George Town, Malaysia

    Lucan Tan Tien Boon & Nor Muzlifah Mahyuddin

Authors
  1. Lucan Tan Tien Boon
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Nor Muzlifah Mahyuddin
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Nor Muzlifah Mahyuddin .

Editor information

Editors and Affiliations

  1. School of Electrical and Electronic Engineering, Universiti Sains Malaysia, Penang, Malaysia

    Nor Muzlifah Mahyuddin

  2. School of Electrical and Electronic Engineering, Universiti Sains Malaysia, Penang, Malaysia

    Nor Rizuan Mat Noor

  3. School of Electrical and Electronic Engineering, Universiti Sains Malaysia, Penang, Malaysia

    Harsa Amylia Mat Sakim

Rights and permissions

Reprints and permissions

Copyright information

© 2022 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Boon, L.T.T., Mahyuddin, N.M. (2022). Speeding Parasitic-Extraction Stage in Layout-Change-Order Validation Cycle Through Net-Tracing and Layout Trimming. In: Mahyuddin, N.M., Mat Noor, N.R., Mat Sakim, H.A. (eds) Proceedings of the 11th International Conference on Robotics, Vision, Signal Processing and Power Applications. Lecture Notes in Electrical Engineering, vol 829. Springer, Singapore. https://doi.org/10.1007/978-981-16-8129-5_15

Download citation

Publish with us

Policies and ethics