Abstract
This paper presents a high efficiency CMOS Power Amplifier (PA) integrated driver based analog pre-distortion (APD) Linearizer. The APD linearization technique has been used as a resolution to enhance the linearity without degrading the efficiency. A 2.45 GHz PA prototype is developed in 180 nm technology. It achieves an input and output return loss of less than –10 dB and power gain more than 20 dB over the operating bandwidth of 2.4 to 2.5 GHz while preserving an unconditional stability performance up to 10 GHz. With maximum output power of 26.7 dBm, the PA delivers 3rd order intercept point (OIP3) of more than 30 dBm with peak power added efficiency (PAE) of 47.2%. The power consumption of 900 mW is achieved with supply voltage of 3.3 V at maximum output power. The fully integrated circuit consumes 2.72 mm2 of area.
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Acknowledgement
This project was supported by CREST grant number PCEDEC/6050415, USM RUI grant 1001/PCEDEC/8014079, MOHE FRGS grant number PCEDEC/6071449 and Silterra Malaysia for the CMOS 180 nm fabrication support.
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Gunasegaran, P., Rajendran, J., Mariappan, S., Aziz, Z.A., Yusof, Y.M. (2022). High Efficiency CMOS Power Amplifier with Integrated Driver Based APD Linearizer. In: Mahyuddin, N.M., Mat Noor, N.R., Mat Sakim, H.A. (eds) Proceedings of the 11th International Conference on Robotics, Vision, Signal Processing and Power Applications. Lecture Notes in Electrical Engineering, vol 829. Springer, Singapore. https://doi.org/10.1007/978-981-16-8129-5_55
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DOI: https://doi.org/10.1007/978-981-16-8129-5_55
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