Multilevel MPSoC Performance Evaluation, ISS Model with Timing and Priority Management

Abstract

To deploy the enormous hardware resources available in Multi-Processor Systems-on-Chip (MPSoC) efficiently, rapidly and accurately, methods of Design Space Exploration (DSE) are needed to evaluate several design choices. In this article, we provide a framework that makes fast simulation and performance evaluation of MPSoC early in flow of design, therefore reducing the time of design. In this platform and within the Transaction Level Modeling (TLM) approach, we present a new definition of ISS level by introducing two complementary modeling ISST and ISSPT sublevels. This later, that we illustrate an arbiter modeling approach that allows a high performance MPSoC communication. A round-robin method is chosen for algorithm arbiter modeling because it is simple, minimizes the communication latency and has an accepted speed-up. Two applications are tested and used to validate our platform: Game of life and JPEG Encoder.

The performance of the proposed approach has been analyzed in MPSoC platform based on multi-MicroBlaze. Results of simulation show with ISSPT sublevels gives a high simulation speedup factor of up to 32 with a negligible performance estimation error margin.