Abstract
The paper reports the development of low power elapsed time counter that tracks a real time and elapsed time. The mixed signal ASIC is implemented in UMC 0.18 µm CMOS mixed signal technology, 3.3 V/1.8 V. This operates at two frequencies 2 MHz and 32.768 kHz. The ultra low power oscillator designed consumes current of 250 nA with minimum frequency variation for all process voltage temperature conditions. The oscillator is simulated using spectra simulator and designed using cadence virtuoso. The area consumed is 0.003064 mm2. The counters count at real time of 1 s. This is achieved by frequency divider which scales down 32.768 kHz to 1 Hz. The entire ASIC is designed using cadence innovus. The die size is 697.5 µm × 697.5 µm. The ASIC is taped out to Taiwan at mini@sic runway for fabrication.
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References
Kalra, P.K., Mudenagudi, U., Banerjee, S.: Space-time super-resolution using graph-cut optimization. IEEE Trans. Pattern Anal. Mach. Intell. 33(5), 995–1008 (2011)
http://www.newark.com/maxim-integrated-products/ds1318e/elapsed-time-counter-binary
Razavi, B.: Design of analog CMOS integrated circuits (2005)
DS1602 elapsed time counter. https://datasheets.maximintegrated.com/en/ds/DS1602.pdf
Mahato, A.K.: Ultra low frequency CMOS ring oscillator design. In: Recent Advances in Engineering and Computational Sciences (RAECS). IEEE (2014)
Suman, S., Bhardwaj, M., Singh, B.: An improved performance ring oscillator design. In: 2012 Second International Conference on Advanced Computing & Communication Technologies (ACCT), pp. 236–239. IEEE (2012)
Keshri, P., Deka, B.: CMOS thyristor based low frequency ring oscillator. Indian Institute of Technology, Kanpur (2007)
Somvanshi, S., Kasavajjala, S.: A low power sub-1 V CMOS voltage reference. EEE Dept, BITS-Pilani, Rajasthan, India and Stanford University, USA (2008)
Choi, M., Lee, I., Jang, T.-K., Blaauw, D., Sylvester, D.: A 23pw, 780 ppm/oC resistor-less current reference using subthreshold MOSFETs. In: ESSCIRC 2014-40th European Solid State Circuits Conference (ESSCIRC), pp. 119–122. IEEE (2014)
Choi, M., Bang, S., Jang, T.-K., Blaauw, D., Sylvester, D.: A 99 nW 70.4 Khz resistive frequency locking on-chip oscillator with 27.4 ppm/oC temperature stability. In: 2015 Symposium on VLSI Circuits (VLSI Circuits), pp. C238–C239. IEEE (2015)
Li, W.-J.: A current compensated reference oscillator. In: 2009 International Symposium on VLSI Design Automation and Test, April 2009
Deva Priya, M., Valarmathi, M.L., Jaya Bharathi, K., Sundarameena, V.: QP - ALAH: QoS provisioned - application layer auxiliary handover in IEEE 802.16e networks. In: Unnikrishnan, S., Surve, S., Bhoir, D. (eds.) ICAC3 2013. CCIS, vol. 361, pp. 366–380. Springer, Heidelberg (2013). https://doi.org/10.1007/978-3-642-36321-4_34
Filanovsky, I., Baltes, H.: CMOS schmitt trigger design. IEEE Trans. Circuits Syst. I: Fundam. Theory Appl. 41(1), 46–49 (1994)
Kalburgi, S., Gupta, D., Holi, S., Saroja, V.S.: Ultra low power low frequency on-chip oscillator for elapsed time counter. In: 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID), pp. 251–256. IEEE (2019). https://doi.org/10.1109/vlsid.2019.00062
Acknowledgment
The authors would like to thank Dr. Anand Bariya, VP SiFive, for his valuable discussion on the mixed signal ASIC flow, and Shri Shripad Annigari for his valuable discussion on circuits. This work is supported under ‘IRP’ scheme by the KLE Technological University.
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Siddamal, S.V., Shirol, S.B., Hiremath, S., Iyer, N.C. (2019). Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS Technology. In: Sengupta, A., Dasgupta, S., Singh, V., Sharma, R., Kumar Vishvakarma, S. (eds) VLSI Design and Test. VDAT 2019. Communications in Computer and Information Science, vol 1066. Springer, Singapore. https://doi.org/10.1007/978-981-32-9767-8_11
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DOI: https://doi.org/10.1007/978-981-32-9767-8_11
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