Clock Pulse Based Foreground Calibration of a Sub-Radix-2 Successive Approximation Register ADC

Abstract

This paper proposes a foreground calibration algorithm of a Successive-Approximation-Register (SAR) ADC using pulsed injection at the analog front-end. Unlike pseudo-random noise injection based calibration, this algorithm uses the clock signal to provide an offset injection at the DAC sub-circuit of the SAR ADC. The DAC portion of the SAR ADC presented in this paper follows sub-radix-2 based architecture. Such architecture produces non-linearity at the ADC output due to obvious result of capacitor mismatch. Non-linearity removal is ensured by extracting the coefficients of the ADC output code. Coefficients are calculated by post processing the ADC output code at the digital calibration block. For calibration, two sets of ADC output codes are collected, at two clock phases. In one clock phases ADC output codes are collected with an incremental offset added and at the other clock phase, same offset value gets subtracted. These collected data are then passed through an LMS algorithm to determine the coefficients. In this paper, behavioral simulation result of a 10-bit SAR ADC shows that after coefficient determination and output code correction, SNDR, SFDR and ENOB improves from 25.85 dB, 34.63 dB and 4.13 bits respectively to 60.60 dB, 78.78 dB and 9.77 bits respectively.