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A CMOS Low Noise Amplifier with Improved Gain

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VLSI Design and Test (VDAT 2019)

Abstract

In this paper, an improved gain CMOS Low Noise Amplifier (LNA) is presented. Here a single stage common source amplifier with common gate as cascode circuit is used to design the LNA. It is having small signal gain of 14.4 dB and covers the bandwidth from 4.47 GHz to 5.41 GHz. It has been observed that at the center frequency of 5 GHz the input and output return loss are −17.98 dB and −15.86 dB respectively. A 1 dB compression point is at −14.85 dBm at 5 GHz input frequency. From 1.8 V supply voltage, 4.67 mA current is drawn.

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Correspondence to Sunanda Ambulker .

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Ambulker, S., Mishra, J.K., Nakhate, S. (2019). A CMOS Low Noise Amplifier with Improved Gain. In: Sengupta, A., Dasgupta, S., Singh, V., Sharma, R., Kumar Vishvakarma, S. (eds) VLSI Design and Test. VDAT 2019. Communications in Computer and Information Science, vol 1066. Springer, Singapore. https://doi.org/10.1007/978-981-32-9767-8_19

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  • DOI: https://doi.org/10.1007/978-981-32-9767-8_19

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-32-9766-1

  • Online ISBN: 978-981-32-9767-8

  • eBook Packages: Computer ScienceComputer Science (R0)

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