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Radiation Hardened by Design Sense Amplifier

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VLSI Design and Test (VDAT 2019)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 1066))

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Abstract

This paper presents a fully symmetrical radiation hardened sense amplifier is designed in and 32 nm FinFET Double gate PTM technology to tolerate single node upset and multiple-node upset.circuit. A 9 pC charge is used at critical node of the sense amplifier to analyse Single Event Transient. The Experimental results on sensing delay, input offset voltage, power comparision and critical charge demonstrated the effectiveness of the proposed scheme.

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Authors and Affiliations

  1. ABV IIITM, Gwalior, 474015, MP, India

    Avinash Verma & Gaurav Kaushal

Authors
  1. Avinash Verma
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  2. Gaurav Kaushal
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Corresponding author

Correspondence to Avinash Verma .

Editor information

Editors and Affiliations

  1. Computer Science and Engineering, Indian Institute of Technology Indore, Indore, India

    Anirban Sengupta

  2. Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, India

    Sudeb Dasgupta

  3. Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India

    Virendra Singh

  4. Department of Electrical Engineering, Indian Institute of Technology Ropar, Rupnagar, India

    Rohit Sharma

  5. Electrical Engineering, Indian Institute of Technology Indore, Indore, India

    Santosh Kumar Vishvakarma

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Verma, A., Kaushal, G. (2019). Radiation Hardened by Design Sense Amplifier. In: Sengupta, A., Dasgupta, S., Singh, V., Sharma, R., Kumar Vishvakarma, S. (eds) VLSI Design and Test. VDAT 2019. Communications in Computer and Information Science, vol 1066. Springer, Singapore. https://doi.org/10.1007/978-981-32-9767-8_20

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  • DOI: https://doi.org/10.1007/978-981-32-9767-8_20

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-32-9766-1

  • Online ISBN: 978-981-32-9767-8

  • eBook Packages: Computer ScienceComputer Science (R0)

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