Abstract
Internet of Things (IoT) is now a growing part of our life. More than 10 billion devices are already connected, and more are expected to be deployed in the next coming years. To provide a practical solution for security, privacy and trust is the main concern for deploying IoT in such a large scale. For security and privacy in IoT, cryptography is the required solutions. AES algorithm is a well known, highly secure and symmetric key algorithm, but the area and power budget of AES makes it unsuitable for IoT Security. In this paper, we have presented a lightweight implementation of AES, with dual-edge triggered S-box. The proposed architecture has been implemented on FPGA as well as in ASIC on 180 nm technology. The proposed architecture uses a 32-bit data path to encrypt 128-bit plain-text with 128-bit cipher-key. ASIC implementation of the proposed architecture results in low-power (122.7 \(\upmu \)W at 1 V) consumption with a reduction in the hardware overhead by 30% and a throughput of 23 Mbps at 10 MHz clock frequency.
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Acknowledgment
The authors would like to thank UGC, Govt. of India under the JRF Scheme for providing financial support (Ref. No. 3548/NET-DEC. 2015). We also extend our sincere gratitude to SMDP-C2SD programme, sponsored by MeitY, Govt. of India providing the required tools to carry out this work and Semiconductor Laboratory (SCL), India for providing PDK.
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Khan, S., Gupta, N., Vishvakarma, A., Chouhan, S.S., Pandey, J.G., Vishvakarma, S.K. (2019). Dual-Edge Triggered Lightweight Implementation of AES for IoT Security. In: Sengupta, A., Dasgupta, S., Singh, V., Sharma, R., Kumar Vishvakarma, S. (eds) VLSI Design and Test. VDAT 2019. Communications in Computer and Information Science, vol 1066. Springer, Singapore. https://doi.org/10.1007/978-981-32-9767-8_26
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DOI: https://doi.org/10.1007/978-981-32-9767-8_26
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