Abstract
The rise in complexity and number of processing cores in SoC has paved way to the development of efficient and structured on-chip communication framework known as Network on Chip (NoC). NoC is embraced as an interconnect solution for the design of large tiled chip multiprocessors (TCMP). It is characterized by performance metrics such as average latency, throughput and power dissipation which depend on underlying network architecture. In this paper, we propose 2L-2D (Two Layer Two dimensional) architecture to enhance performance of conventional buffered 2D mesh NoC where two identical layers of 8 \(\times \) 8 meshes are stacked one on top of the other. 2L-2D uses conventional 5-port virtual channel router (VCR) architecture and vertical interconnections are made by utilizing unused ports at edge routers only. Experimental results indicate that our proposed approach improves throughput and network saturation point whereas average flit latency and power dissipation is considerably reduced when compared with standard 5-port 2D mesh and torus designs.
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Kunthara, R.G., Neethu, K., James, R.K., Sleeba, S.Z., Warrier, T.S., Jose, J. (2019). 2L-2D Routing for Buffered Mesh Network-on-Chip. In: Sengupta, A., Dasgupta, S., Singh, V., Sharma, R., Kumar Vishvakarma, S. (eds) VLSI Design and Test. VDAT 2019. Communications in Computer and Information Science, vol 1066. Springer, Singapore. https://doi.org/10.1007/978-981-32-9767-8_27
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