Abstract
Achieving complete design verification by formal methods remains a daunting goal to date. With advancements in model checkers and other formal techniques, large designs can be verified in a partial or semi-formal manner. However, it is well known that exhaustive exploration of design state space is still prohibitive. In this paper, we revisit the concept of guided state space exploration which holds the promise of complete formal verification. Since it is not trivial to devise guidance strategies in an automatic manner, identification of the guidance hints becomes very crucial for a directed traversal of the state space. This directed traversal can ultimately reduce the time spent in formal verification and also assist in better design debugging. We propose a methodology for identification of such guideposts and utilize them for debugging purpose. Our goal is to achieve faster counter-example generation by the usage of guideposts. Experiments on a complex design show that guidance hints identified with the proposed methodology provide significant gains during model checking for different error traces.
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Notes
- 1.
The signal which goes high when the FIFO is full.
- 2.
For this particular case, WP2 happens to be there in the property as well. We had to use broad_fifo.data_o in property 1 to ensure that the final output signals are generated by the requests 41’h83 and 41’h483, and not one of the many other possible requests which might give the same output values for cbus_cmd0_o and cbus_addr_o at MESI OUTPUT.
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Vineesh, V.S., Kumar, B., Adhaduk, J. (2019). Identification of Effective Guidance Hints for Better Design Debugging by Formal Methods. In: Sengupta, A., Dasgupta, S., Singh, V., Sharma, R., Kumar Vishvakarma, S. (eds) VLSI Design and Test. VDAT 2019. Communications in Computer and Information Science, vol 1066. Springer, Singapore. https://doi.org/10.1007/978-981-32-9767-8_35
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