Abstract
In this paper, we propose a two-step fault-tolerant approach to address the faults occurred in cores. In the first stage, a Particle Swarm Optimization (PSO) based approach has been proposed for the fault-tolerant mapping of multiple applications on to the mesh based reconfigurable architecture by introducing spare cores and a heuristic has been proposed for the reconfiguration in the second stage. The proposed approach has been experimented by taking several benchmark applications into consideration. Communication cost comparisons have been carried out by taking the failed cores as user input and the experimental results show that our approach could get improvements in terms of communication cost after reconfiguration compared to before reconfiguration by providing fault-tolerance to the design.
This work is partially supported by the research project No. ECR/2016/001389 Dt. 06/03/2017, sponsored by the SERB, Government of India.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Multi-application network-on-chip design using global mapping and local reconfiguration. ACM Trans. Reconfigurable Technol. Syst. 7(2), 7:1–7:24 (2014)
Benini, L., Micheli, G.D.: Networks on chips: a new SoC paradigm. Computer 35(1), 70–78 (2002)
Constantinescu, C.: Trends and challenges in VLSI circuit reliability. IEEE Micro 23(4), 14–19 (2003)
Dally, W.J., Towles, B.: Route packets, not wires: on-chip inteconnection networks. In: Proceedings of the 38th Annual Design Automation Conference, DAC 2001. pp. 684–689. ACM, New York (2001)
Dick, R.P., Rhodes, D.L., Wolf, W.: TGFF: task graphs for free. In: Proceedings of the Sixth International Workshop on Hardware/Software Codesign, (CODES/CASHE 1998), pp. 97–101, March 1998
Islam, A.: Technology scaling and its side effects. In: 2015 19th International Symposium on VLSI Design and Test, p. 1, June 2015
Kennedy, J., Eberhart, R.: Particle swarm optimization. In: IEEE International Conference on Neural Networks, Proceedings, vol. 4, pp. 1942–1948, November 1995
Modarressi, M., Tavakkol, A., Sarbazi-Azad, H.: Application-aware topology reconfiguration for on-chip networks. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 19(11), 2010–2022 (2011)
Parikh, R., Bertacco, V.: Resource conscious diagnosis and reconfiguration for noc permanent faults. IEEE Trans. Comput. 65(7), 2241–2256 (2016)
Pasricha, S., Dutt, N., Ben-Romdhane, M.: Using TLM for exploring bus-based SoC communication architectures. In: 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP 2005), pp. 79–85, July 2005
Rana, V., Atienza, D., Santambrogio, M.D., Sciuto, D., De Micheli, G.: A reconfigurable network-on-chip architecture for optimal multi-processor SoC communication. In: Piguet, C., Reis, R., Soudris, D. (eds.) VLSI-SoC 2008. IAICT, vol. 313, pp. 232–250. Springer, Heidelberg (2010). https://doi.org/10.1007/978-3-642-12267-5_13
Sahu, P.K., Chattopadhyay, S.: A survey on application mapping strategies for network-on-chip design. J. Syst. Archit. 59(1), 60–76 (2013)
Stensgaard, M.B., Sparsø J.: Renoc: a network-on-chip architecture with reconfigurable topology. In: Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), pp. 55–64, April 2008
Trivino, F., Alfaro, F.J., Sánchez, J.L., Flich, J.: Noc reconfiguration for CMP virtualization. In: 2011 IEEE 10th International Symposium on Network Computing and Applications, pp. 219–222, August 2011
Wang, J., Ebrahimi, M., Huang, L., Jantsch, A., Li, G.: Design of fault-tolerant and reliable networks-on-chip. In: 2015 IEEE Computer Society Annual Symposium on VLSI, pp. 545–550, July 2015
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Veda Bhanu, P., Kulkarni, P.V., Avadhanam, S.P., Soumya, J., Cenkeramaddi, L.R. (2019). Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture. In: Sengupta, A., Dasgupta, S., Singh, V., Sharma, R., Kumar Vishvakarma, S. (eds) VLSI Design and Test. VDAT 2019. Communications in Computer and Information Science, vol 1066. Springer, Singapore. https://doi.org/10.1007/978-981-32-9767-8_37
Download citation
DOI: https://doi.org/10.1007/978-981-32-9767-8_37
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-32-9766-1
Online ISBN: 978-981-32-9767-8
eBook Packages: Computer ScienceComputer Science (R0)