Abstract
This paper presents a study and analysis of 10T SRAM (static random-access memory) cell and also comparison has been done with conventional 6T SRAM and it also gives good Read stability and Write Margin with 34.21% and 33.33% respectively and less power. Proposed design is used as a part of memory with single purpose devices which requires low power consumption and reliability because memories are integrated part of digital circuits. Analysis and design of this circuit is done by using cadence tool at 180 nm technology. Simulation-based results are represented in this paper.
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Singh, K., Gamad, R.S., Bansod, P.P. (2019). Design and Analysis for Power Reduction with High SNM of 10T SRAM Cell. In: Sengupta, A., Dasgupta, S., Singh, V., Sharma, R., Kumar Vishvakarma, S. (eds) VLSI Design and Test. VDAT 2019. Communications in Computer and Information Science, vol 1066. Springer, Singapore. https://doi.org/10.1007/978-981-32-9767-8_45
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DOI: https://doi.org/10.1007/978-981-32-9767-8_45
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