Abstract
This work presents the design and calibration of an ultra-low power 14-bit 10 KS/s fully differential split SAR ADC. The integrated transient response of the ADC shows a settling accuracy of 32 \(\upmu \)V within 50 \(\upmu \)s while consuming only 19.5 \(\upmu \)W power. The simulated post-layout spectrum yields an SNDR of 84.5 dB with an effective linearity of 13.8 bits. The ADC occupies a total area of 2.5 mm \(\times \) 2.5 mm when implemented in the SCL 0.18 \(\upmu \)m 2P4M CMOS processes. The implementation is shown to be highly power efficient with an energy figure of merit of 140 fJ/conversion step. The challenges faced during the full chip implementation of the ADC and techniques used to overcome them at various levels of design hierarchy are discussed in details.
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Mekkattillam, Y., Mohapatra, S., Mohapatra, N.R. (2019). Design and Calibration of 14-bit 10 KS/s Low Power SAR ADC for Bio-medical Applications. In: Sengupta, A., Dasgupta, S., Singh, V., Sharma, R., Kumar Vishvakarma, S. (eds) VLSI Design and Test. VDAT 2019. Communications in Computer and Information Science, vol 1066. Springer, Singapore. https://doi.org/10.1007/978-981-32-9767-8_49
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DOI: https://doi.org/10.1007/978-981-32-9767-8_49
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