Abstract
This paper presents a new write assist 12T SRAM cell with data dependent power supply with read decoupled circuit to enhance the read stability and write ability at the low supply voltage. The proposed 12T cell is design to isolate the read path for enhancing the read static noise margin. Stacking effect is used to control leakage current and improved write static noise margin of the cell. As compared with the 6T SRAM cell, the proposed cell offers 8.66\(\times \), 3.4\(\times \), and 1.53\(\times \) higher write, read and hold stability respectively at 0.4 V supply voltage. Our evaluation indicates that the leakage and write power of the proposed cell is reduced by 59% and 99.98% respectively as compared to the conventional 6T cell. For a better perspective of the proposed cell, a compound figure of merit has been introduced and it is found that the proposed cell has 38.048% higher FOM as compared to 6T SRAM cell. All the implementations have been performed using the industry standard 180 nm CMOS technology.
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Acknowledgment
The authors would like to thank Special Manpower Development Program for Chips to System Design (SMDP-C2SD) research project of Department of Electronics and Information technology (DeitY) under Ministry of Communication and Information Technology, Government of India to provide the lab facilities.
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Gupta, N., Prasad, J., Kumar, R.S., Rajput, G., Vishvakarma, S.K. (2019). A Robust Low-Power Write-Assist Data-Dependent-Power-Supplied 12T SRAM Cell. In: Sengupta, A., Dasgupta, S., Singh, V., Sharma, R., Kumar Vishvakarma, S. (eds) VLSI Design and Test. VDAT 2019. Communications in Computer and Information Science, vol 1066. Springer, Singapore. https://doi.org/10.1007/978-981-32-9767-8_52
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DOI: https://doi.org/10.1007/978-981-32-9767-8_52
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