Abstract
This paper presents a new ultra low power 8T SRAM cell with data dependent power supply circuit with read decoupled technique to enhance the read stability and sleep transistor is used to reduce the leakage power at the low supply voltage. The data dependent circuit reduces the dynamic power and enhances the write ability drastically. The area penalty is also very less due to the absence of access transistor. As compared with the 6T SRAM cell, the proposed cell offers 3.13%, 89.56%, and 68.35% higher write, read and hold stability respectively at 0.4 V supply voltage. Our evaluation indicates that the leakage and read power of the proposed cell is reduced by 98.75% and 99.74% respectively as compared to the conventional 6T cell and read delay and write PDP is reduced by 63.41% and 88.17%, respectively as compared to 6T cell. For a better perspective of the proposed cell, a compound stability to energy ratio has been introduced and it is found that the SER of proposed cell has very high as compared to 6T SRAM cell. All the implementations have been performed using the industry standard 65 nm CMOS technology.
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Acknowledgment
The authors would like to thank Special Manpower Development Program for Chips to System Design (SMDP-C2SD) research project of Department of Electronics and Information technology (DeitY) under Ministry of Communication and Information Technology, Government of India to provide the lab facilities.
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Gupta, N., Gupta, T., Khan, S., Vishwakarma, A., Vishvakarma, S.K. (2019). Low Leakage Highly Stable Robust Ultra Low Power 8T SRAM Cell. In: Sengupta, A., Dasgupta, S., Singh, V., Sharma, R., Kumar Vishvakarma, S. (eds) VLSI Design and Test. VDAT 2019. Communications in Computer and Information Science, vol 1066. Springer, Singapore. https://doi.org/10.1007/978-981-32-9767-8_53
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DOI: https://doi.org/10.1007/978-981-32-9767-8_53
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